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authorJason Ekstrand <[email protected]>2019-07-26 17:41:59 -0500
committerJason Ekstrand <[email protected]>2019-07-29 11:34:18 -0500
commit7c1b39cf18481f0d15f3ffb1130da4479032d76a (patch)
tree6af5095c034ca166e4a5555aec4049563fcf7616 /src/intel
parent463164b325d1a9d6b05f4e459af04b2e8df29dbe (diff)
isl/formats: R8G8B8_UNORM_SRGB isn't supported on HSW
On Haswell, the format works but it doesn't properly do an sRGB decode. It appears to act identically to R8G8B8_UNORM. Only Vulkan uses this format so this only affects Vulkan on HSW. Cc: [email protected] Reviewed-by: Eric Engestrom <[email protected]>
Diffstat (limited to 'src/intel')
-rw-r--r--src/intel/isl/isl_format.c6
1 files changed, 5 insertions, 1 deletions
diff --git a/src/intel/isl/isl_format.c b/src/intel/isl/isl_format.c
index b429e7779a4..9847f231923 100644
--- a/src/intel/isl/isl_format.c
+++ b/src/intel/isl/isl_format.c
@@ -294,7 +294,11 @@ static const struct surface_format_info format_info[] = {
SF( 70, 70, x, x, x, x, x, x, x, x, x, x, BC7_UNORM_SRGB)
SF( 70, 70, x, x, x, x, x, x, x, x, x, x, BC6H_UF16)
SF( x, x, x, x, x, x, x, x, x, x, x, x, PLANAR_420_8)
- SF( 75, 75, x, x, x, x, x, x, x, x, x, x, R8G8B8_UNORM_SRGB)
+ /* The format enum for R8G8B8_UNORM_SRGB first shows up in the HSW PRM but
+ * empirical testing indicates that it doesn't actually sRGB decode and
+ * acts identical to R8G8B8_UNORM. It does work on gen8+.
+ */
+ SF( 80, 80, x, x, x, x, x, x, x, x, x, x, R8G8B8_UNORM_SRGB)
SF( 80, 80, x, x, x, x, x, x, x, x, x, x, ETC1_RGB8)
SF( 80, 80, x, x, x, x, x, x, x, x, x, x, ETC2_RGB8)
SF( 80, 80, x, x, x, x, x, x, x, x, x, x, EAC_R11)