intel/isl: Add the maximum surface size limit

V2: Use 2^31 bytes (2GB) surface size limit on pre-gen9 and
    2^38 bytes for gen9+.

Signed-off-by: Anuj Phogat <[email protected]>
Reviewed-by: Nanley Chery <[email protected]>
(cherry picked from commit c07271fef095164c8bcfb54fdc95567c3774a866)

1 files changed, 22 insertions, 0 deletions

diff --git a/src/intel/isl/isl.c b/src/intel/isl/isl.c
index 32aa698eb87..8cb139c61b2 100644
--- a/src/intel/isl/isl.c
+++ b/src/intel/isl/isl.c
@@ -1398,6 +1398,28 @@ isl_surf_init_s(const struct isl_device *dev,
       base_alignment = MAX(info->min_alignment, tile_size);
    }
 
+   if (ISL_DEV_GEN(dev) < 9) {
+      /* From the Broadwell PRM Vol 5, Surface Layout:
+       *
+       *    "In addition to restrictions on maximum height, width, and depth,
+       *     surfaces are also restricted to a maximum size in bytes. This
+       *     maximum is 2 GB for all products and all surface types."
+       *
+       * This comment is applicable to all Pre-gen9 platforms.
+       */
+      if (size > (uint64_t) 1 << 31)
+         return false;
+   } else {
+      /* From the Skylake PRM Vol 5, Maximum Surface Size in Bytes:
+       *    "In addition to restrictions on maximum height, width, and depth,
+       *     surfaces are also restricted to a maximum size of 2^38 bytes.
+       *     All pixels within the surface must be contained within 2^38 bytes
+       *     of the base address."
+       */
+      if (size > (uint64_t) 1 << 38)
+         return false;
+   }
+
    *surf = (struct isl_surf) {
       .dim = info->dim,
       .dim_layout = dim_layout,