diff options
| author | Jason Ekstrand <[email protected]> | 2018-02-16 12:03:22 -0800 |
|---|---|---|
| committer | Dylan Baker <[email protected]> | 2020-03-18 10:28:19 -0700 |
| commit | 44e9b6ab620b4020d13205187045557c4721aba4 (patch) | |
| tree | 5d18053ff6ae8f0e15e8dbff48e6d11bbdc145f5 /src/intel | |
| parent | 8bc42bf9dbc9de02ec720ebcc314aefba1ab9583 (diff) | |
anv: Do end-of-pipe sync around MCS/CCS ops instead of CS stall
v2: Do end-of-pipe sync after clear depth stencil too (Jason).
v3: Also do end-of-pipe sync before clear depth stencil too (Jason).
Reviewed-by: Rafael Antognolli <[email protected]>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4005>
(cherry picked from commit 3ca3050de57e60e86c1e3ccfa9d57689ffc5a820)
Diffstat (limited to 'src/intel')
| -rw-r--r-- | src/intel/vulkan/anv_blorp.c | 12 | ||||
| -rw-r--r-- | src/intel/vulkan/genX_cmd_buffer.c | 4 |
2 files changed, 8 insertions, 8 deletions
diff --git a/src/intel/vulkan/anv_blorp.c b/src/intel/vulkan/anv_blorp.c index a9e664c3310..c2fed12aa1d 100644 --- a/src/intel/vulkan/anv_blorp.c +++ b/src/intel/vulkan/anv_blorp.c @@ -1580,7 +1580,7 @@ anv_image_clear_depth_stencil(struct anv_cmd_buffer *cmd_buffer, * cache before rendering to it. */ cmd_buffer->state.pending_pipe_bits |= - ANV_PIPE_DEPTH_CACHE_FLUSH_BIT | ANV_PIPE_CS_STALL_BIT; + ANV_PIPE_DEPTH_CACHE_FLUSH_BIT | ANV_PIPE_END_OF_PIPE_SYNC_BIT; blorp_clear_depth_stencil(&batch, &depth, &stencil, level, base_layer, layer_count, @@ -1597,7 +1597,7 @@ anv_image_clear_depth_stencil(struct anv_cmd_buffer *cmd_buffer, * cache before someone starts trying to do stencil on it. */ cmd_buffer->state.pending_pipe_bits |= - ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT | ANV_PIPE_CS_STALL_BIT; + ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT | ANV_PIPE_END_OF_PIPE_SYNC_BIT; struct blorp_surf stencil_shadow; if ((aspects & VK_IMAGE_ASPECT_STENCIL_BIT) && @@ -1778,7 +1778,7 @@ anv_image_mcs_op(struct anv_cmd_buffer *cmd_buffer, * that it is completed before any additional drawing occurs. */ cmd_buffer->state.pending_pipe_bits |= - ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT | ANV_PIPE_CS_STALL_BIT; + ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT | ANV_PIPE_END_OF_PIPE_SYNC_BIT; switch (mcs_op) { case ISL_AUX_OP_FAST_CLEAR: @@ -1797,7 +1797,7 @@ anv_image_mcs_op(struct anv_cmd_buffer *cmd_buffer, } cmd_buffer->state.pending_pipe_bits |= - ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT | ANV_PIPE_CS_STALL_BIT; + ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT | ANV_PIPE_END_OF_PIPE_SYNC_BIT; blorp_batch_finish(&batch); } @@ -1859,7 +1859,7 @@ anv_image_ccs_op(struct anv_cmd_buffer *cmd_buffer, * that it is completed before any additional drawing occurs. */ cmd_buffer->state.pending_pipe_bits |= - ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT | ANV_PIPE_CS_STALL_BIT; + ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT | ANV_PIPE_END_OF_PIPE_SYNC_BIT; switch (ccs_op) { case ISL_AUX_OP_FAST_CLEAR: @@ -1883,7 +1883,7 @@ anv_image_ccs_op(struct anv_cmd_buffer *cmd_buffer, } cmd_buffer->state.pending_pipe_bits |= - ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT | ANV_PIPE_CS_STALL_BIT; + ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT | ANV_PIPE_END_OF_PIPE_SYNC_BIT; blorp_batch_finish(&batch); } diff --git a/src/intel/vulkan/genX_cmd_buffer.c b/src/intel/vulkan/genX_cmd_buffer.c index 587fdd3a095..d3abc98511c 100644 --- a/src/intel/vulkan/genX_cmd_buffer.c +++ b/src/intel/vulkan/genX_cmd_buffer.c @@ -1315,7 +1315,7 @@ transition_color_buffer(struct anv_cmd_buffer *cmd_buffer, * we do any more rendering or clearing. */ cmd_buffer->state.pending_pipe_bits |= - ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT | ANV_PIPE_CS_STALL_BIT; + ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT | ANV_PIPE_END_OF_PIPE_SYNC_BIT; for (uint32_t l = 0; l < level_count; l++) { uint32_t level = base_level + l; @@ -1351,7 +1351,7 @@ transition_color_buffer(struct anv_cmd_buffer *cmd_buffer, } cmd_buffer->state.pending_pipe_bits |= - ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT | ANV_PIPE_CS_STALL_BIT; + ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT | ANV_PIPE_END_OF_PIPE_SYNC_BIT; } /** |