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authorAnuj Phogat <[email protected]>2017-05-26 15:40:55 -0700
committerAnuj Phogat <[email protected]>2018-02-16 11:10:32 -0800
commita86c0a08df1bbd65374fa9fc42c289329ca5e70a (patch)
treec7800c012f8f35e85c2edf4dffd7ec322b13693f /src/intel
parentcd5fc634a8af5f6ff32ab1824f296fea09b18639 (diff)
anv/icl: Don't use DISPATCH_MODE_SIMD4X2
Signed-off-by: Anuj Phogat <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
Diffstat (limited to 'src/intel')
-rw-r--r--src/intel/vulkan/genX_pipeline.c5
1 files changed, 5 insertions, 0 deletions
diff --git a/src/intel/vulkan/genX_pipeline.c b/src/intel/vulkan/genX_pipeline.c
index 85391c93cad..89cbe293b86 100644
--- a/src/intel/vulkan/genX_pipeline.c
+++ b/src/intel/vulkan/genX_pipeline.c
@@ -1253,10 +1253,15 @@ emit_3dstate_hs_te_ds(struct anv_pipeline *pipeline,
tes_prog_data->base.base.dispatch_grf_start_reg;
#if GEN_GEN >= 8
+#if GEN_GEN < 11
ds.DispatchMode =
tes_prog_data->base.dispatch_mode == DISPATCH_MODE_SIMD8 ?
DISPATCH_MODE_SIMD8_SINGLE_PATCH :
DISPATCH_MODE_SIMD4X2;
+#else
+ assert(tes_prog_data->base.dispatch_mode == DISPATCH_MODE_SIMD8);
+ ds.DispatchMode = DISPATCH_MODE_SIMD8_SINGLE_PATCH;
+#endif
ds.UserClipDistanceClipTestEnableBitmask =
tes_prog_data->base.clip_distance_mask;