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authorD Scott Phillips <[email protected]>2020-04-30 17:38:33 +0000
committerD Scott Phillips <[email protected]>2020-05-01 08:48:22 -0700
commit7bd15135a6dc105939a3e1c349217e6346dcf729 (patch)
treee2fce3193854e1591059fb64a6c33cd8f7df1a3a /src/intel
parent7eb2bc8f52f0e4aaaac1add6236841484dabeecf (diff)
intel/fs: Update location of Render Target Array Index for gen12
Render Target Array Index has moved from R0.0[26:16] to R1.1[26:16] on gen12. Fixes dEQP-VK.multiview.input_attachments.* Cc: <[email protected]> Reviewed-by: Francisco Jerez <[email protected]> Reviewed-by: Caio Marcelo de Oliveira Filho <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4836>
Diffstat (limited to 'src/intel')
-rw-r--r--src/intel/compiler/brw_fs_nir.cpp10
1 files changed, 9 insertions, 1 deletions
diff --git a/src/intel/compiler/brw_fs_nir.cpp b/src/intel/compiler/brw_fs_nir.cpp
index e29ba744d8b..e3149f6254c 100644
--- a/src/intel/compiler/brw_fs_nir.cpp
+++ b/src/intel/compiler/brw_fs_nir.cpp
@@ -3162,7 +3162,15 @@ fs_visitor::nir_emit_gs_intrinsic(const fs_builder &bld,
static fs_reg
fetch_render_target_array_index(const fs_builder &bld)
{
- if (bld.shader->devinfo->gen >= 6) {
+ if (bld.shader->devinfo->gen >= 12) {
+ /* The render target array index is provided in the thread payload as
+ * bits 26:16 of r1.1.
+ */
+ const fs_reg idx = bld.vgrf(BRW_REGISTER_TYPE_UD);
+ bld.AND(idx, brw_uw1_reg(BRW_GENERAL_REGISTER_FILE, 1, 3),
+ brw_imm_uw(0x7ff));
+ return idx;
+ } else if (bld.shader->devinfo->gen >= 6) {
/* The render target array index is provided in the thread payload as
* bits 26:16 of r0.0.
*/