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authorFrancisco Jerez <[email protected]>2017-01-09 14:14:02 -0800
committerJason Ekstrand <[email protected]>2018-06-28 13:19:38 -0700
commit7144247c2c349e7013ec33cfb46eb3e84b63007a (patch)
treeb72fff25075aaf567ad3aa2459df015a30e33a38 /src/intel
parent37c1df28c993c9b065672688b20dca167eb9f04b (diff)
intel/fs: Fix fs_builder::sample_mask_reg() for 32-wide FS dispatch.
Reviewed-by: Jason Ekstrand <[email protected]> Reviewed-by: Matt Turner <[email protected]>
Diffstat (limited to 'src/intel')
-rw-r--r--src/intel/compiler/brw_fs_builder.h6
1 files changed, 3 insertions, 3 deletions
diff --git a/src/intel/compiler/brw_fs_builder.h b/src/intel/compiler/brw_fs_builder.h
index 4203c8c27c3..7bee2aa0b9b 100644
--- a/src/intel/compiler/brw_fs_builder.h
+++ b/src/intel/compiler/brw_fs_builder.h
@@ -235,14 +235,14 @@ namespace brw {
src_reg
sample_mask_reg() const
{
- assert(shader->stage != MESA_SHADER_FRAGMENT ||
- group() + dispatch_width() <= 16);
if (shader->stage != MESA_SHADER_FRAGMENT) {
return brw_imm_d(0xffffffff);
} else if (brw_wm_prog_data(shader->stage_prog_data)->uses_kill) {
return brw_flag_reg(0, 1);
} else {
- return retype(brw_vec1_grf(1, 7), BRW_REGISTER_TYPE_UD);
+ assert(shader->devinfo->gen >= 6 && dispatch_width() <= 16);
+ return retype(brw_vec1_grf((_group >= 16 ? 2 : 1), 7),
+ BRW_REGISTER_TYPE_UD);
}
}