diff options
| author | Jason Ekstrand <[email protected]> | 2019-02-08 17:56:52 -0600 |
|---|---|---|
| committer | Jason Ekstrand <[email protected]> | 2019-04-19 19:56:42 +0000 |
| commit | 2edf29b933564d4f1aae80b91f674f1175f91625 (patch) | |
| tree | 8ee215d444bad8228fa701f0cbbf839a3cde943d /src/intel | |
| parent | bd56ce8ce5045a181b9fc8a7f24251931e343f9c (diff) | |
intel,nir: Lower TXD with a bindless sampler
When we have a bindless sampler, we need an instruction header. Even in
SIMD8, this pushes the instruction over the sampler message size maximum
of 11 registers. Instead, we have to lower TXD to TXL.
Reviewed-by: Lionel Landwerlin <[email protected]>
Reviewed-by: Caio Marcelo de Oliveira Filho <[email protected]>
Diffstat (limited to 'src/intel')
| -rw-r--r-- | src/intel/compiler/brw_nir.c | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/src/intel/compiler/brw_nir.c b/src/intel/compiler/brw_nir.c index 4aa7905e4c4..e0a393fc298 100644 --- a/src/intel/compiler/brw_nir.c +++ b/src/intel/compiler/brw_nir.c @@ -949,6 +949,7 @@ brw_nir_apply_sampler_key(nir_shader *nir, { const struct gen_device_info *devinfo = compiler->devinfo; nir_lower_tex_options tex_options = { + .lower_txd_clamp_bindless_sampler = true, .lower_txd_clamp_if_sampler_index_not_lt_16 = true, }; |