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authorSamuel Pitoiset <[email protected]>2019-03-22 09:24:57 +0100
committerSamuel Pitoiset <[email protected]>2019-03-22 19:41:46 +0100
commit23d30f4099fac0e1fcbd7adf315a186f553e48d2 (patch)
treec96617c3df226f62b78eefbce74d1b9c1277be3c /src/intel
parent6ae5797243a6ace4d65088620291884be2a09fa6 (diff)
spirv,nir: lower frexp_exp/frexp_sig inside a new NIR pass
This lowering isn't needed for RADV because AMDGCN has two instructions. It will be disabled for RADV in an upcoming series. While we are at it, factorize a little bit. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
Diffstat (limited to 'src/intel')
-rw-r--r--src/intel/vulkan/anv_pipeline.c2
1 files changed, 2 insertions, 0 deletions
diff --git a/src/intel/vulkan/anv_pipeline.c b/src/intel/vulkan/anv_pipeline.c
index e9319f5efef..90942a4524a 100644
--- a/src/intel/vulkan/anv_pipeline.c
+++ b/src/intel/vulkan/anv_pipeline.c
@@ -226,6 +226,8 @@ anv_shader_compile_to_nir(struct anv_device *device,
NIR_PASS_V(nir, nir_lower_io_to_temporaries,
entry_point->impl, true, false);
+ NIR_PASS_V(nir, nir_lower_frexp);
+
/* Vulkan uses the separate-shader linking model */
nir->info.separate_shader = true;