diff options
| author | Anuj Phogat <[email protected]> | 2017-05-26 15:42:02 -0700 |
|---|---|---|
| committer | Anuj Phogat <[email protected]> | 2018-02-16 11:10:32 -0800 |
| commit | cd5fc634a8af5f6ff32ab1824f296fea09b18639 (patch) | |
| tree | ba99f9f9ddb3500eff82a7cfc5963b3ee4033ec9 /src/intel | |
| parent | 6e3940b3cfd7d0e55dfe1f3db3ec8751ac216af6 (diff) | |
anv/icl: Don't use SingleVertexDispatch
Signed-off-by: Anuj Phogat <[email protected]>
Reviewed-by: Jason Ekstrand <[email protected]>
Diffstat (limited to 'src/intel')
| -rw-r--r-- | src/intel/vulkan/genX_pipeline.c | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/src/intel/vulkan/genX_pipeline.c b/src/intel/vulkan/genX_pipeline.c index 784559380db..85391c93cad 100644 --- a/src/intel/vulkan/genX_pipeline.c +++ b/src/intel/vulkan/genX_pipeline.c @@ -1135,7 +1135,9 @@ emit_3dstate_vs(struct anv_pipeline *pipeline) #endif assert(!vs_prog_data->base.base.use_alt_mode); +#if GEN_GEN < 11 vs.SingleVertexDispatch = false; +#endif vs.VectorMaskEnable = false; vs.SamplerCount = get_sampler_count(vs_bin); vs.BindingTableEntryCount = get_binding_table_entry_count(vs_bin); |