diff options
author | Anuj Phogat <[email protected]> | 2017-06-13 11:08:48 -0700 |
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committer | Anuj Phogat <[email protected]> | 2017-06-22 14:17:45 -0700 |
commit | c17e214a6bf1da97c78fa7a6192cb1b498b773a1 (patch) | |
tree | fcf34c9504468e39ea9f0f22ed332fb1ffddec1a /src/intel | |
parent | bf1d2c37c6a3e48dcdecd3559d6026f684d67ee0 (diff) |
anv/cnl: Don't set FloatBlendOptimizationEnable{Mask}
This field is remove from CACHE_MODE_1 register in gen10.
Signed-off-by: Anuj Phogat <[email protected]>
Reviewed-by: Jason Ekstrand <[email protected]>
Diffstat (limited to 'src/intel')
-rw-r--r-- | src/intel/vulkan/genX_state.c | 9 |
1 files changed, 6 insertions, 3 deletions
diff --git a/src/intel/vulkan/genX_state.c b/src/intel/vulkan/genX_state.c index 00c4105a825..7a16ec06f71 100644 --- a/src/intel/vulkan/genX_state.c +++ b/src/intel/vulkan/genX_state.c @@ -55,10 +55,13 @@ genX(init_device_state)(struct anv_device *device) #if GEN_GEN >= 9 uint32_t cache_mode_1; anv_pack_struct(&cache_mode_1, GENX(CACHE_MODE_1), - .PartialResolveDisableInVC = true, - .PartialResolveDisableInVCMask = true, +#if GEN_GEN == 9 .FloatBlendOptimizationEnable = true, - .FloatBlendOptimizationEnableMask = true); + .FloatBlendOptimizationEnableMask = true, +#endif + .PartialResolveDisableInVC = true, + .PartialResolveDisableInVCMask = true); + anv_batch_emit(&batch, GENX(MI_LOAD_REGISTER_IMM), lri) { lri.RegisterOffset = GENX(CACHE_MODE_1_num); lri.DataDWord = cache_mode_1; |