diff options
| author | Ian Romanick <[email protected]> | 2018-06-18 16:11:55 -0700 |
|---|---|---|
| committer | Ian Romanick <[email protected]> | 2018-12-17 13:47:06 -0800 |
| commit | 378f9967710e9145f2a4f8eee89d87badbe0e6ea (patch) | |
| tree | eea53659babbc84c15da3357ab7c01f615c2d3a3 /src/intel | |
| parent | 8fb8ebfbb05d3323481c8ba6d320b3a3580bad99 (diff) | |
nir/opt_peephole_select: Don't peephole_select expensive math instructions
On some GPUs, especially older Intel GPUs, some math instructions are
very expensive. On those architectures, don't reduce flow control to a
csel if one of the branches contains one of these expensive math
instructions.
This prevents a bunch of cycle count regressions on pre-Gen6 platforms
with a later patch (intel/compiler: More peephole select for pre-Gen6).
v2: Remove stray #if block. Noticed by Thomas.
Signed-off-by: Ian Romanick <[email protected]>
Reviewed-by: Thomas Helland <[email protected]>
Reviewed-by: Lionel Landwerlin <[email protected]>
Diffstat (limited to 'src/intel')
| -rw-r--r-- | src/intel/compiler/brw_nir.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/intel/compiler/brw_nir.c b/src/intel/compiler/brw_nir.c index 3e547daf78a..8a5665076b9 100644 --- a/src/intel/compiler/brw_nir.c +++ b/src/intel/compiler/brw_nir.c @@ -589,9 +589,9 @@ brw_nir_optimize(nir_shader *nir, const struct brw_compiler *compiler, const bool is_vec4_tessellation = !is_scalar && (nir->info.stage == MESA_SHADER_TESS_CTRL || nir->info.stage == MESA_SHADER_TESS_EVAL); - OPT(nir_opt_peephole_select, 0, !is_vec4_tessellation); + OPT(nir_opt_peephole_select, 0, !is_vec4_tessellation, false); if (compiler->devinfo->gen >= 6) - OPT(nir_opt_peephole_select, 1, !is_vec4_tessellation); + OPT(nir_opt_peephole_select, 1, !is_vec4_tessellation, true); OPT(nir_opt_intrinsics); OPT(nir_opt_idiv_const, 32); |