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authorAnuj Phogat <[email protected]>2017-11-10 14:22:18 -0800
committerAnuj Phogat <[email protected]>2017-11-14 13:23:18 -0800
commit72a239266b84033e539283d50ca0b3c50e630463 (patch)
tree6513ea97eabec5aadae41604d815ba368bda53ab /src/intel/vulkan
parentaacf1943c0a13b8ec565d9f256552608d35c3b4a (diff)
intel/genxml: Add Cache Mode SubSlice Register to gen10.xml
Signed-off-by: Anuj Phogat <[email protected]> Reviewed-by: Rafael Antognolli <[email protected]>
Diffstat (limited to 'src/intel/vulkan')
0 files changed, 0 insertions, 0 deletions