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authorLionel Landwerlin <[email protected]>2019-01-17 17:00:14 +0000
committerLionel Landwerlin <[email protected]>2019-01-19 15:45:41 +0000
commit3c4c18341aafbdd0c24665a56d0af32b1e4dc981 (patch)
tree11b8f3e43720705042695cb165682dc2ce4b5f13 /src/intel/vulkan
parent6ca652faf368427e3e6d57ef5456f78203b8207e (diff)
anv: narrow flushing of the render target to buffer writes
In commit 9a7b3199037ac4 ("anv/query: flush render target before copying results") we tracked all the render target writes to apply a flushes in the vkCopyQueryResults(). But we can narrow this down to only when we write a buffer (which is the only input of vkCopyQueryResults). v2: Drop newer render target write flags introduce by 1952fd8d2ce905 ("anv: Implement VK_EXT_conditional_rendering for gen 7.5+") Signed-off-by: Lionel Landwerlin <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]> (v1)
Diffstat (limited to 'src/intel/vulkan')
-rw-r--r--src/intel/vulkan/anv_blorp.c8
-rw-r--r--src/intel/vulkan/anv_private.h9
-rw-r--r--src/intel/vulkan/genX_blorp_exec.c1
-rw-r--r--src/intel/vulkan/genX_cmd_buffer.c14
-rw-r--r--src/intel/vulkan/genX_gpu_memcpy.c1
-rw-r--r--src/intel/vulkan/genX_query.c2
6 files changed, 15 insertions, 20 deletions
diff --git a/src/intel/vulkan/anv_blorp.c b/src/intel/vulkan/anv_blorp.c
index 827f224c278..aafe56baab9 100644
--- a/src/intel/vulkan/anv_blorp.c
+++ b/src/intel/vulkan/anv_blorp.c
@@ -475,6 +475,8 @@ void anv_CmdCopyImageToBuffer(
copy_buffer_to_image(cmd_buffer, dst_buffer, src_image, srcImageLayout,
regionCount, pRegions, false);
+
+ cmd_buffer->state.pending_pipe_bits |= ANV_PIPE_RENDER_TARGET_BUFFER_WRITES;
}
static bool
@@ -682,6 +684,8 @@ void anv_CmdCopyBuffer(
}
blorp_batch_finish(&batch);
+
+ cmd_buffer->state.pending_pipe_bits |= ANV_PIPE_RENDER_TARGET_BUFFER_WRITES;
}
void anv_CmdUpdateBuffer(
@@ -737,6 +741,8 @@ void anv_CmdUpdateBuffer(
}
blorp_batch_finish(&batch);
+
+ cmd_buffer->state.pending_pipe_bits |= ANV_PIPE_RENDER_TARGET_BUFFER_WRITES;
}
void anv_CmdFillBuffer(
@@ -824,6 +830,8 @@ void anv_CmdFillBuffer(
}
blorp_batch_finish(&batch);
+
+ cmd_buffer->state.pending_pipe_bits |= ANV_PIPE_RENDER_TARGET_BUFFER_WRITES;
}
void anv_CmdClearColorImage(
diff --git a/src/intel/vulkan/anv_private.h b/src/intel/vulkan/anv_private.h
index 0299febc1d5..1384f86d384 100644
--- a/src/intel/vulkan/anv_private.h
+++ b/src/intel/vulkan/anv_private.h
@@ -1790,11 +1790,12 @@ enum anv_pipe_bits {
ANV_PIPE_NEEDS_CS_STALL_BIT = (1 << 21),
/* This bit does not exist directly in PIPE_CONTROL. It means that render
- * target operations are ongoing. Some operations like copies on the
- * command streamer might need to be aware of this to trigger the
- * appropriate stall before they can proceed with the copy.
+ * target operations related to transfer commands with VkBuffer as
+ * destination are ongoing. Some operations like copies on the command
+ * streamer might need to be aware of this to trigger the appropriate stall
+ * before they can proceed with the copy.
*/
- ANV_PIPE_RENDER_TARGET_WRITES = (1 << 22),
+ ANV_PIPE_RENDER_TARGET_BUFFER_WRITES = (1 << 22),
};
#define ANV_PIPE_FLUSH_BITS ( \
diff --git a/src/intel/vulkan/genX_blorp_exec.c b/src/intel/vulkan/genX_blorp_exec.c
index 6b1f471850d..e9c85d56d5f 100644
--- a/src/intel/vulkan/genX_blorp_exec.c
+++ b/src/intel/vulkan/genX_blorp_exec.c
@@ -268,5 +268,4 @@ genX(blorp_exec)(struct blorp_batch *batch,
cmd_buffer->state.gfx.vb_dirty = ~0;
cmd_buffer->state.gfx.dirty = ~0;
cmd_buffer->state.push_constants_dirty = ~0;
- cmd_buffer->state.pending_pipe_bits |= ANV_PIPE_RENDER_TARGET_WRITES;
}
diff --git a/src/intel/vulkan/genX_cmd_buffer.c b/src/intel/vulkan/genX_cmd_buffer.c
index e69c169b9ba..2d94d85d141 100644
--- a/src/intel/vulkan/genX_cmd_buffer.c
+++ b/src/intel/vulkan/genX_cmd_buffer.c
@@ -1811,7 +1811,7 @@ genX(cmd_buffer_apply_pipe_flushes)(struct anv_cmd_buffer *cmd_buffer)
* saying that render target writes are ongoing.
*/
if (bits & ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT)
- bits &= ~(ANV_PIPE_RENDER_TARGET_WRITES);
+ bits &= ~(ANV_PIPE_RENDER_TARGET_BUFFER_WRITES);
bits &= ~(ANV_PIPE_FLUSH_BITS | ANV_PIPE_CS_STALL_BIT);
}
@@ -2828,8 +2828,6 @@ void genX(CmdDraw)(
prim.StartInstanceLocation = firstInstance;
prim.BaseVertexLocation = 0;
}
-
- cmd_buffer->state.pending_pipe_bits |= ANV_PIPE_RENDER_TARGET_WRITES;
}
void genX(CmdDrawIndexed)(
@@ -2873,8 +2871,6 @@ void genX(CmdDrawIndexed)(
prim.StartInstanceLocation = firstInstance;
prim.BaseVertexLocation = vertexOffset;
}
-
- cmd_buffer->state.pending_pipe_bits |= ANV_PIPE_RENDER_TARGET_WRITES;
}
/* Auto-Draw / Indirect Registers */
@@ -3012,8 +3008,6 @@ void genX(CmdDrawIndirect)(
offset += stride;
}
-
- cmd_buffer->state.pending_pipe_bits |= ANV_PIPE_RENDER_TARGET_WRITES;
}
void genX(CmdDrawIndexedIndirect)(
@@ -3057,8 +3051,6 @@ void genX(CmdDrawIndexedIndirect)(
offset += stride;
}
-
- cmd_buffer->state.pending_pipe_bits |= ANV_PIPE_RENDER_TARGET_WRITES;
}
#define TMP_DRAW_COUNT_REG MI_ALU_REG14
@@ -3218,8 +3210,6 @@ void genX(CmdDrawIndirectCountKHR)(
offset += stride;
}
-
- cmd_buffer->state.pending_pipe_bits |= ANV_PIPE_RENDER_TARGET_WRITES;
}
void genX(CmdDrawIndexedIndirectCountKHR)(
@@ -3280,8 +3270,6 @@ void genX(CmdDrawIndexedIndirectCountKHR)(
offset += stride;
}
-
- cmd_buffer->state.pending_pipe_bits |= ANV_PIPE_RENDER_TARGET_WRITES;
}
static VkResult
diff --git a/src/intel/vulkan/genX_gpu_memcpy.c b/src/intel/vulkan/genX_gpu_memcpy.c
index 8f3700c80e3..7ef14dd14ef 100644
--- a/src/intel/vulkan/genX_gpu_memcpy.c
+++ b/src/intel/vulkan/genX_gpu_memcpy.c
@@ -299,5 +299,4 @@ genX(cmd_buffer_so_memcpy)(struct anv_cmd_buffer *cmd_buffer,
}
cmd_buffer->state.gfx.dirty |= ANV_CMD_DIRTY_PIPELINE;
- cmd_buffer->state.pending_pipe_bits |= ANV_PIPE_RENDER_TARGET_WRITES;
}
diff --git a/src/intel/vulkan/genX_query.c b/src/intel/vulkan/genX_query.c
index 71b7a1352f0..638d6d8b4b2 100644
--- a/src/intel/vulkan/genX_query.c
+++ b/src/intel/vulkan/genX_query.c
@@ -733,7 +733,7 @@ void genX(CmdCopyQueryPoolResults)(
* to ensure proper ordering of the commands from the 3d pipe and the
* command streamer.
*/
- if (cmd_buffer->state.pending_pipe_bits & ANV_PIPE_RENDER_TARGET_WRITES) {
+ if (cmd_buffer->state.pending_pipe_bits & ANV_PIPE_RENDER_TARGET_BUFFER_WRITES) {
cmd_buffer->state.pending_pipe_bits |=
ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT;
}