diff options
| author | Anuj Phogat <[email protected]> | 2018-08-27 16:16:58 -0700 |
|---|---|---|
| committer | Anuj Phogat <[email protected]> | 2018-09-21 14:40:04 -0700 |
| commit | 5eb173304bd1cebdde0617bcc42cd4dca0b8c880 (patch) | |
| tree | 9b14cd353d164d806db7b26db73377ec450accf4 /src/intel/vulkan | |
| parent | afb7c6b301ea4275d64498a0b62a908777cb9b24 (diff) | |
anv/icl: Set Enabled Texel Offset Precision Fix bit
h/w specification requires this bit to be always set.
Suggested-by: Kenneth Graunke <[email protected]>
Signed-off-by: Anuj Phogat <[email protected]>
Reviewed-by: Kenneth Graunke <[email protected]>
Diffstat (limited to 'src/intel/vulkan')
| -rw-r--r-- | src/intel/vulkan/genX_state.c | 14 |
1 files changed, 14 insertions, 0 deletions
diff --git a/src/intel/vulkan/genX_state.c b/src/intel/vulkan/genX_state.c index 4a175b9234d..aa5bce5a801 100644 --- a/src/intel/vulkan/genX_state.c +++ b/src/intel/vulkan/genX_state.c @@ -172,6 +172,20 @@ genX(init_device_state)(struct anv_device *device) lri.RegisterOffset = GENX(SAMPLER_MODE_num); lri.DataDWord = sampler_mode; } + + /* Bit 1 "Enabled Texel Offset Precision Fix" must be set in + * HALF_SLICE_CHICKEN7 register. + */ + uint32_t half_slice_chicken7; + anv_pack_struct(&half_slice_chicken7, GENX(HALF_SLICE_CHICKEN7), + .EnabledTexelOffsetPrecisionFix = true, + .EnabledTexelOffsetPrecisionFixMask = true); + + anv_batch_emit(&batch, GENX(MI_LOAD_REGISTER_IMM), lri) { + lri.RegisterOffset = GENX(HALF_SLICE_CHICKEN7_num); + lri.DataDWord = half_slice_chicken7; + } + #endif /* Set the "CONSTANT_BUFFER Address Offset Disable" bit, so |