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authorNanley Chery <[email protected]>2017-04-27 16:22:03 -0700
committerJason Ekstrand <[email protected]>2017-06-07 08:54:54 -0700
commited5801864ede0a04fb5fa80bf9ffea40e5c0e022 (patch)
tree9525f823aaabb17e4156a94842497f3463c002e3 /src/intel/vulkan
parentfbd8a33f61b7fef320ed11730fe6d474bb897120 (diff)
anv/blorp: Move the depth cache flush outside of BLORP
Signed-off-by: Nanley Chery <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
Diffstat (limited to 'src/intel/vulkan')
-rw-r--r--src/intel/vulkan/anv_blorp.c16
1 files changed, 16 insertions, 0 deletions
diff --git a/src/intel/vulkan/anv_blorp.c b/src/intel/vulkan/anv_blorp.c
index d94a2f89fa5..a869eebc241 100644
--- a/src/intel/vulkan/anv_blorp.c
+++ b/src/intel/vulkan/anv_blorp.c
@@ -1323,6 +1323,22 @@ anv_cmd_buffer_clear_subpass(struct anv_cmd_buffer *cmd_buffer)
clear_depth, clear_stencil,
clear_att.clearValue.
depthStencil.stencil);
+
+ /* From the SKL PRM, Depth Buffer Clear:
+ *
+ * Depth Buffer Clear Workaround
+ * Depth buffer clear pass using any of the methods (WM_STATE,
+ * 3DSTATE_WM or 3DSTATE_WM_HZ_OP) must be followed by a
+ * PIPE_CONTROL command with DEPTH_STALL bit and Depth FLUSH bits
+ * “set” before starting to render. DepthStall and DepthFlush are
+ * not needed between consecutive depth clear passes nor is it
+ * required if the depth-clear pass was done with “full_surf_clear”
+ * bit set in the 3DSTATE_WM_HZ_OP.
+ */
+ if (clear_depth) {
+ cmd_buffer->state.pending_pipe_bits |=
+ ANV_PIPE_DEPTH_CACHE_FLUSH_BIT | ANV_PIPE_DEPTH_STALL_BIT;
+ }
}
}