anv: Switch over to the macros in genxml

13 files changed, 122 insertions, 275 deletions

diff --git a/src/intel/vulkan/Makefile.am b/src/intel/vulkan/Makefile.am
index ccd98856b4b..6be4f9fb427 100644
--- a/src/intel/vulkan/Makefile.am
+++ b/src/intel/vulkan/Makefile.am
@@ -108,7 +108,7 @@ libanv_gen7_la_SOURCES =                                \
 	gen7_cmd_buffer.c				\
 	gen7_pipeline.c                                 \
 	gen7_state.c
-libanv_gen7_la_CFLAGS = $(libvulkan_intel_la_CFLAGS) -DANV_GENx10=70
+libanv_gen7_la_CFLAGS = $(libvulkan_intel_la_CFLAGS) -DGEN_VERSIONx10=70
 
 libanv_gen75_la_SOURCES =                               \
 	genX_cmd_buffer.c				\
@@ -116,7 +116,7 @@ libanv_gen75_la_SOURCES =                               \
 	gen7_cmd_buffer.c				\
 	gen7_pipeline.c                                 \
 	gen7_state.c
-libanv_gen75_la_CFLAGS = $(libvulkan_intel_la_CFLAGS) -DANV_GENx10=75
+libanv_gen75_la_CFLAGS = $(libvulkan_intel_la_CFLAGS) -DGEN_VERSIONx10=75
 
 libanv_gen8_la_SOURCES =                               	\
 	genX_cmd_buffer.c				\
@@ -124,7 +124,7 @@ libanv_gen8_la_SOURCES =                               	\
 	gen8_cmd_buffer.c				\
 	gen8_pipeline.c					\
 	gen8_state.c
-libanv_gen8_la_CFLAGS = $(libvulkan_intel_la_CFLAGS) -DANV_GENx10=80
+libanv_gen8_la_CFLAGS = $(libvulkan_intel_la_CFLAGS) -DGEN_VERSIONx10=80
 
 libanv_gen9_la_SOURCES =                               	\
 	genX_cmd_buffer.c				\
@@ -132,7 +132,7 @@ libanv_gen9_la_SOURCES =                               	\
 	gen8_cmd_buffer.c				\
 	gen8_pipeline.c					\
 	gen8_state.c
-libanv_gen9_la_CFLAGS = $(libvulkan_intel_la_CFLAGS) -DANV_GENx10=90
+libanv_gen9_la_CFLAGS = $(libvulkan_intel_la_CFLAGS) -DGEN_VERSIONx10=90
 
 if HAVE_EGL_PLATFORM_WAYLAND
 BUILT_SOURCES += \
diff --git a/src/intel/vulkan/anv_gen_macros.h b/src/intel/vulkan/anv_gen_macros.h
deleted file mode 100644
index ef2ecd55a9b..00000000000
--- a/src/intel/vulkan/anv_gen_macros.h
+++ /dev/null
@@ -1,146 +0,0 @@
-/*
- * Copyright © 2015 Intel Corporation
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice (including the next
- * paragraph) shall be included in all copies or substantial portions of the
- * Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
- * IN THE SOFTWARE.
- */
-
-#pragma once
-
-/* Macros for handling per-gen compilation.
- *
- * The prefixing macros GENX() and genX() automatically prefix whatever you
- * give them by GENX_ or genX_  where X is the gen number.
- *
- * You can declare a function to be used on some range of gens like this:
- *
- * GENX_FUNC(GEN7, GEN75) void
- * genX(my_function_name)(args...)
- * {
- *    // Do stuff
- * }
- *
- * If the file is compiled for any set of gens containing gen7 and gen75,
- * the function will effectively only get compiled twice as
- * gen7_my_function_nmae and gen75_my_function_name.  The function has to
- * be compilable on all gens, but it will become a static inline that gets
- * discarded by the compiler on all gens not in range.
- *
- * You can do pseudo-runtime checks in your function such as
- *
- * if (ANV_GEN > 8 || ANV_IS_HASWELL) {
- *    // Do something
- * }
- *
- * The contents of the if statement must be valid regardless of gen, but
- * the if will get compiled away on everything except haswell.
- *
- * For places where you really do have a compile-time conflict, you can
- * use preprocessor logic:
- *
- * #if (ANV_GEN > 8 || ANV_IS_HASWELL)
- *    // Do something
- * #endif
- *
- * However, it is strongly recommended that the former be used whenever
- * possible.
- */
-
-/* Base macro defined on the command line.  If we don't have this, we can't
- * do anything.
- */
-#ifdef ANV_GENx10
-
-/* Gen checking macros */
-#define ANV_GEN ((ANV_GENx10) / 10)
-#define ANV_IS_HASWELL ((ANV_GENx10) == 75)
-
-/* Prefixing macros */
-#if (ANV_GENx10 == 70)
-#  define GENX(X) GEN7_##X
-#  define genX(x) gen7_##x
-#elif (ANV_GENx10 == 75)
-#  define GENX(X) GEN75_##X
-#  define genX(x) gen75_##x
-#elif (ANV_GENx10 == 80)
-#  define GENX(X) GEN8_##X
-#  define genX(x) gen8_##x
-#elif (ANV_GENx10 == 90)
-#  define GENX(X) GEN9_##X
-#  define genX(x) gen9_##x
-#else
-#  error "Need to add prefixing macros for your gen"
-#endif
-
-/* Macros for comparing gens */
-#if (ANV_GENx10 >= 70)
-#define __ANV_GEN_GE_GEN7(T, F) T
-#else
-#define __ANV_GEN_GE_GEN7(T, F) F
-#endif
-
-#if (ANV_GENx10 <= 70)
-#define __ANV_GEN_LE_GEN7(T, F) T
-#else
-#define __ANV_GEN_LE_GEN7(T, F) F
-#endif
-
-#if (ANV_GENx10 >= 75)
-#define __ANV_GEN_GE_GEN75(T, F) T
-#else
-#define __ANV_GEN_GE_GEN75(T, F) F
-#endif
-
-#if (ANV_GENx10 <= 75)
-#define __ANV_GEN_LE_GEN75(T, F) T
-#else
-#define __ANV_GEN_LE_GEN75(T, F) F
-#endif
-
-#if (ANV_GENx10 >= 80)
-#define __ANV_GEN_GE_GEN8(T, F) T
-#else
-#define __ANV_GEN_GE_GEN8(T, F) F
-#endif
-
-#if (ANV_GENx10 <= 80)
-#define __ANV_GEN_LE_GEN8(T, F) T
-#else
-#define __ANV_GEN_LE_GEN8(T, F) F
-#endif
-
-#if (ANV_GENx10 >= 90)
-#define __ANV_GEN_GE_GEN9(T, F) T
-#else
-#define __ANV_GEN_GE_GEN9(T, F) F
-#endif
-
-#if (ANV_GENx10 <= 90)
-#define __ANV_GEN_LE_GEN9(T, F) T
-#else
-#define __ANV_GEN_LE_GEN9(T, F) F
-#endif
-
-#define __ANV_GEN_IN_RANGE(start, end, T, F) \
-   __ANV_GEN_GE_##start(__ANV_GEN_LE_##end(T, F), F)
-
-/* Declares a function as static inlind if it's not in range */
-#define GENX_FUNC(start, end) __ANV_GEN_IN_RANGE(start, end, , static inline)
-
-#endif /* ANV_GENx10 */
diff --git a/src/intel/vulkan/anv_private.h b/src/intel/vulkan/anv_private.h
index ba86333525e..479f3826135 100644
--- a/src/intel/vulkan/anv_private.h
+++ b/src/intel/vulkan/anv_private.h
@@ -60,7 +60,6 @@ typedef uint32_t xcb_window_t;
 #include <vulkan/vk_icd.h>
 
 #include "anv_entrypoints.h"
-#include "anv_gen_macros.h"
 #include "brw_context.h"
 #include "isl/isl.h"
 
diff --git a/src/intel/vulkan/gen7_cmd_buffer.c b/src/intel/vulkan/gen7_cmd_buffer.c
index 23327ec0724..e96400d5b6c 100644
--- a/src/intel/vulkan/gen7_cmd_buffer.c
+++ b/src/intel/vulkan/gen7_cmd_buffer.c
@@ -29,8 +29,8 @@
 
 #include "anv_private.h"
 
-#include "genxml/gen7_pack.h"
-#include "genxml/gen75_pack.h"
+#include "genxml/gen_macros.h"
+#include "genxml/genX_pack.h"
 
 static uint32_t
 cmd_buffer_flush_push_constants(struct anv_cmd_buffer *cmd_buffer)
@@ -55,7 +55,7 @@ cmd_buffer_flush_push_constants(struct anv_cmd_buffer *cmd_buffer)
       if (state.offset == 0)
          continue;
 
-      anv_batch_emit(&cmd_buffer->batch, GEN7_3DSTATE_CONSTANT_VS,
+      anv_batch_emit(&cmd_buffer->batch, GENX(3DSTATE_CONSTANT_VS),
                      ._3DCommandSubOpcode = push_constant_opcodes[stage],
                      .ConstantBody = {
                         .PointerToConstantBuffer0 = { .offset = state.offset },
@@ -95,7 +95,7 @@ genX(cmd_buffer_emit_descriptor_pointers)(struct anv_cmd_buffer *cmd_buffer,
    anv_foreach_stage(s, stages) {
       if (cmd_buffer->state.samplers[s].alloc_size > 0) {
          anv_batch_emit(&cmd_buffer->batch,
-                        GEN7_3DSTATE_SAMPLER_STATE_POINTERS_VS,
+                        GENX(3DSTATE_SAMPLER_STATE_POINTERS_VS),
                         ._3DCommandSubOpcode  = sampler_state_opcodes[s],
                         .PointertoVSSamplerState = cmd_buffer->state.samplers[s].offset);
       }
@@ -103,7 +103,7 @@ genX(cmd_buffer_emit_descriptor_pointers)(struct anv_cmd_buffer *cmd_buffer,
       /* Always emit binding table pointers if we're asked to, since on SKL
        * this is what flushes push constants. */
       anv_batch_emit(&cmd_buffer->batch,
-                     GEN7_3DSTATE_BINDING_TABLE_POINTERS_VS,
+                     GENX(3DSTATE_BINDING_TABLE_POINTERS_VS),
                      ._3DCommandSubOpcode  = binding_table_opcodes[s],
                      .PointertoVSBindingTable = cmd_buffer->state.binding_tables[s].offset);
    }
@@ -168,6 +168,7 @@ clamp_int64(int64_t x, int64_t min, int64_t max)
       return max;
 }
 
+#if GEN_GEN == 7 && !GEN_IS_HASWELL
 static void
 emit_scissor_state(struct anv_cmd_buffer *cmd_buffer,
                    uint32_t count, const VkRect2D *scissors)
@@ -214,8 +215,8 @@ emit_scissor_state(struct anv_cmd_buffer *cmd_buffer,
       anv_state_clflush(scissor_state);
 }
 
-GENX_FUNC(GEN7, GEN7) void
-genX(cmd_buffer_emit_scissor)(struct anv_cmd_buffer *cmd_buffer)
+void
+gen7_cmd_buffer_emit_scissor(struct anv_cmd_buffer *cmd_buffer)
 {
    if (cmd_buffer->state.dynamic.scissor.count > 0) {
       emit_scissor_state(cmd_buffer, cmd_buffer->state.dynamic.scissor.count,
@@ -232,6 +233,7 @@ genX(cmd_buffer_emit_scissor)(struct anv_cmd_buffer *cmd_buffer)
                          });
    }
 }
+#endif
 
 static const uint32_t vk_to_gen_index_type[] = {
    [VK_INDEX_TYPE_UINT16]                       = INDEX_WORD,
@@ -253,7 +255,7 @@ void genX(CmdBindIndexBuffer)(
    ANV_FROM_HANDLE(anv_buffer, buffer, _buffer);
 
    cmd_buffer->state.dirty |= ANV_CMD_DIRTY_INDEX_BUFFER;
-   if (ANV_IS_HASWELL)
+   if (GEN_IS_HASWELL)
       cmd_buffer->state.restart_index = restart_index_for_type[indexType];
    cmd_buffer->state.gen7.index_buffer = buffer;
    cmd_buffer->state.gen7.index_type = vk_to_gen_index_type[indexType];
@@ -306,20 +308,22 @@ flush_compute_descriptor_set(struct anv_cmd_buffer *cmd_buffer)
 
    struct anv_state state =
       anv_state_pool_emit(&device->dynamic_state_pool,
-                          GEN7_INTERFACE_DESCRIPTOR_DATA, 64,
+                          GENX(INTERFACE_DESCRIPTOR_DATA), 64,
                           .KernelStartPointer = pipeline->cs_simd,
                           .BindingTablePointer = surfaces.offset,
                           .SamplerStatePointer = samplers.offset,
                           .ConstantURBEntryReadLength =
                              push_constant_regs,
+#if !GEN_IS_HASWELL
                           .ConstantURBEntryReadOffset = 0,
+#endif
                           .BarrierEnable = cs_prog_data->uses_barrier,
                           .SharedLocalMemorySize = slm_size,
                           .NumberofThreadsinGPGPUThreadGroup =
                              pipeline->cs_thread_width_max);
 
-   const uint32_t size = GEN7_INTERFACE_DESCRIPTOR_DATA_length * sizeof(uint32_t);
-   anv_batch_emit(&cmd_buffer->batch, GEN7_MEDIA_INTERFACE_DESCRIPTOR_LOAD,
+   const uint32_t size = GENX(INTERFACE_DESCRIPTOR_DATA_length) * sizeof(uint32_t);
+   anv_batch_emit(&cmd_buffer->batch, GENX(MEDIA_INTERFACE_DESCRIPTOR_LOAD),
                   .InterfaceDescriptorTotalLength = size,
                   .InterfaceDescriptorDataStartAddress = state.offset);
 
@@ -335,7 +339,7 @@ genX(cmd_buffer_flush_compute_state)(struct anv_cmd_buffer *cmd_buffer)
    assert(pipeline->active_stages == VK_SHADER_STAGE_COMPUTE_BIT);
 
    if (cmd_buffer->state.current_pipeline != GPGPU) {
-      anv_batch_emit(&cmd_buffer->batch, GEN7_PIPELINE_SELECT,
+      anv_batch_emit(&cmd_buffer->batch, GENX(PIPELINE_SELECT),
                      .PipelineSelection = GPGPU);
       cmd_buffer->state.current_pipeline = GPGPU;
    }
@@ -371,16 +375,16 @@ genX(cmd_buffer_flush_state)(struct anv_cmd_buffer *cmd_buffer)
       const uint32_t num_dwords = 1 + num_buffers * 4;
 
       p = anv_batch_emitn(&cmd_buffer->batch, num_dwords,
-                          GEN7_3DSTATE_VERTEX_BUFFERS);
+                          GENX(3DSTATE_VERTEX_BUFFERS));
       uint32_t vb, i = 0;
       for_each_bit(vb, vb_emit) {
          struct anv_buffer *buffer = cmd_buffer->state.vertex_bindings[vb].buffer;
          uint32_t offset = cmd_buffer->state.vertex_bindings[vb].offset;
 
-         struct GEN7_VERTEX_BUFFER_STATE state = {
+         struct GENX(VERTEX_BUFFER_STATE) state = {
             .VertexBufferIndex = vb,
             .BufferAccessType = pipeline->instancing_enable[vb] ? INSTANCEDATA : VERTEXDATA,
-            .VertexBufferMemoryObjectControlState = GEN7_MOCS,
+            .VertexBufferMemoryObjectControlState = GENX(MOCS),
             .AddressModifyEnable = true,
             .BufferPitch = pipeline->binding_stride[vb],
             .BufferStartingAddress = { buffer->bo, buffer->offset + offset },
@@ -388,7 +392,7 @@ genX(cmd_buffer_flush_state)(struct anv_cmd_buffer *cmd_buffer)
             .InstanceDataStepRate = 1
          };
 
-         GEN7_VERTEX_BUFFER_STATE_pack(&cmd_buffer->batch, &p[1 + i * 4], &state);
+         GENX(VERTEX_BUFFER_STATE_pack)(&cmd_buffer->batch, &p[1 + i * 4], &state);
          i++;
       }
    }
@@ -416,7 +420,7 @@ genX(cmd_buffer_flush_state)(struct anv_cmd_buffer *cmd_buffer)
        *    PIPE_CONTROL needs to be sent before any combination of VS
        *    associated 3DSTATE."
        */
-      anv_batch_emit(&cmd_buffer->batch, GEN7_PIPE_CONTROL,
+      anv_batch_emit(&cmd_buffer->batch, GENX(PIPE_CONTROL),
                      .DepthStallEnable = true,
                      .PostSyncOperation = WriteImmediateData,
                      .Address = { &cmd_buffer->device->workaround_bo, 0 });
@@ -456,9 +460,9 @@ genX(cmd_buffer_flush_state)(struct anv_cmd_buffer *cmd_buffer)
          isl_surf_get_depth_format(&cmd_buffer->device->isl_dev,
                                    &image->depth_surface.isl) : D16_UNORM;
 
-      uint32_t sf_dw[GEN7_3DSTATE_SF_length];
-      struct GEN7_3DSTATE_SF sf = {
-         GEN7_3DSTATE_SF_header,
+      uint32_t sf_dw[GENX(3DSTATE_SF_length)];
+      struct GENX(3DSTATE_SF) sf = {
+         GENX(3DSTATE_SF_header),
          .DepthBufferSurfaceFormat = depth_format,
          .LineWidth = cmd_buffer->state.dynamic.line_width,
          .GlobalDepthOffsetEnableSolid = enable_bias,
@@ -468,7 +472,7 @@ genX(cmd_buffer_flush_state)(struct anv_cmd_buffer *cmd_buffer)
          .GlobalDepthOffsetScale = cmd_buffer->state.dynamic.depth_bias.slope,
          .GlobalDepthOffsetClamp = cmd_buffer->state.dynamic.depth_bias.clamp
       };
-      GEN7_3DSTATE_SF_pack(NULL, sf_dw, &sf);
+      GENX(3DSTATE_SF_pack)(NULL, sf_dw, &sf);
 
       anv_batch_emit_merge(&cmd_buffer->batch, sf_dw, pipeline->gen7.sf);
    }
@@ -477,9 +481,9 @@ genX(cmd_buffer_flush_state)(struct anv_cmd_buffer *cmd_buffer)
                                   ANV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE)) {
       struct anv_state cc_state =
          anv_cmd_buffer_alloc_dynamic_state(cmd_buffer,
-                                            GEN7_COLOR_CALC_STATE_length * 4,
+                                            GENX(COLOR_CALC_STATE_length) * 4,
                                             64);
-      struct GEN7_COLOR_CALC_STATE cc = {
+      struct GENX(COLOR_CALC_STATE) cc = {
          .BlendConstantColorRed = cmd_buffer->state.dynamic.blend_constants[0],
          .BlendConstantColorGreen = cmd_buffer->state.dynamic.blend_constants[1],
          .BlendConstantColorBlue = cmd_buffer->state.dynamic.blend_constants[2],
@@ -489,12 +493,12 @@ genX(cmd_buffer_flush_state)(struct anv_cmd_buffer *cmd_buffer)
          .BackFaceStencilReferenceValue =
             cmd_buffer->state.dynamic.stencil_reference.back,
       };
-      GEN7_COLOR_CALC_STATE_pack(NULL, cc_state.map, &cc);
+      GENX(COLOR_CALC_STATE_pack)(NULL, cc_state.map, &cc);
       if (!cmd_buffer->device->info.has_llc)
          anv_state_clflush(cc_state);
 
       anv_batch_emit(&cmd_buffer->batch,
-                     GEN7_3DSTATE_CC_STATE_POINTERS,
+                     GENX(3DSTATE_CC_STATE_POINTERS),
                      .ColorCalcStatePointer = cc_state.offset);
    }
 
@@ -502,12 +506,12 @@ genX(cmd_buffer_flush_state)(struct anv_cmd_buffer *cmd_buffer)
                                   ANV_CMD_DIRTY_RENDER_TARGETS |
                                   ANV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK |
                                   ANV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK)) {
-      uint32_t depth_stencil_dw[GEN7_DEPTH_STENCIL_STATE_length];
+      uint32_t depth_stencil_dw[GENX(DEPTH_STENCIL_STATE_length)];
 
       const struct anv_image_view *iview =
          anv_cmd_buffer_get_depth_stencil_view(cmd_buffer);
 
-      struct GEN7_DEPTH_STENCIL_STATE depth_stencil = {
+      struct GENX(DEPTH_STENCIL_STATE) depth_stencil = {
          .StencilBufferWriteEnable = iview && (iview->aspect_mask & VK_IMAGE_ASPECT_STENCIL_BIT),
 
          .StencilTestMask =
@@ -520,15 +524,15 @@ genX(cmd_buffer_flush_state)(struct anv_cmd_buffer *cmd_buffer)
          .BackfaceStencilWriteMask =
             cmd_buffer->state.dynamic.stencil_write_mask.back & 0xff,
       };
-      GEN7_DEPTH_STENCIL_STATE_pack(NULL, depth_stencil_dw, &depth_stencil);
+      GENX(DEPTH_STENCIL_STATE_pack)(NULL, depth_stencil_dw, &depth_stencil);
 
       struct anv_state ds_state =
          anv_cmd_buffer_merge_dynamic(cmd_buffer, depth_stencil_dw,
                                       pipeline->gen7.depth_stencil_state,
-                                      GEN7_DEPTH_STENCIL_STATE_length, 64);
+                                      GENX(DEPTH_STENCIL_STATE_length), 64);
 
       anv_batch_emit(&cmd_buffer->batch,
-                     GEN7_3DSTATE_DEPTH_STENCIL_STATE_POINTERS,
+                     GENX(3DSTATE_DEPTH_STENCIL_STATE_POINTERS),
                      .PointertoDEPTH_STENCIL_STATE = ds_state.offset);
    }
 
@@ -538,16 +542,18 @@ genX(cmd_buffer_flush_state)(struct anv_cmd_buffer *cmd_buffer)
       struct anv_buffer *buffer = cmd_buffer->state.gen7.index_buffer;
       uint32_t offset = cmd_buffer->state.gen7.index_offset;
 
-      if (ANV_IS_HASWELL) {
-         anv_batch_emit(&cmd_buffer->batch, GEN75_3DSTATE_VF,
-                        .IndexedDrawCutIndexEnable = pipeline->primitive_restart,
-                        .CutIndex = cmd_buffer->state.restart_index);
-      }
+#if GEN_IS_HASWELL
+      anv_batch_emit(&cmd_buffer->batch, GEN75_3DSTATE_VF,
+                     .IndexedDrawCutIndexEnable = pipeline->primitive_restart,
+                     .CutIndex = cmd_buffer->state.restart_index);
+#endif
 
-      anv_batch_emit(&cmd_buffer->batch, GEN7_3DSTATE_INDEX_BUFFER,
+      anv_batch_emit(&cmd_buffer->batch, GENX(3DSTATE_INDEX_BUFFER),
+#if !GEN_IS_HASWELL
                      .CutIndexEnable = pipeline->primitive_restart,
+#endif
                      .IndexFormat = cmd_buffer->state.gen7.index_type,
-                     .MemoryObjectControlState = GEN7_MOCS,
+                     .MemoryObjectControlState = GENX(MOCS),
                      .BufferStartingAddress = { buffer->bo, buffer->offset + offset },
                      .BufferEndingAddress = { buffer->bo, buffer->offset + buffer->size });
    }
diff --git a/src/intel/vulkan/gen7_pipeline.c b/src/intel/vulkan/gen7_pipeline.c
index 7c054fa56d5..009a79ac815 100644
--- a/src/intel/vulkan/gen7_pipeline.c
+++ b/src/intel/vulkan/gen7_pipeline.c
@@ -29,8 +29,8 @@
 
 #include "anv_private.h"
 
-#include "genxml/gen7_pack.h"
-#include "genxml/gen75_pack.h"
+#include "genxml/gen_macros.h"
+#include "genxml/genX_pack.h"
 
 #include "genX_pipeline_util.h"
 
@@ -39,8 +39,8 @@ gen7_emit_rs_state(struct anv_pipeline *pipeline,
                    const VkPipelineRasterizationStateCreateInfo *info,
                    const struct anv_graphics_pipeline_create_info *extra)
 {
-   struct GEN7_3DSTATE_SF sf = {
-      GEN7_3DSTATE_SF_header,
+   struct GENX(3DSTATE_SF) sf = {
+      GENX(3DSTATE_SF_header),
 
       /* LegacyGlobalDepthBiasEnable */
 
@@ -69,7 +69,7 @@ gen7_emit_rs_state(struct anv_pipeline *pipeline,
       .PointWidth                               = 1.0,
    };
 
-   GEN7_3DSTATE_SF_pack(NULL, &pipeline->gen7.sf, &sf);
+   GENX(3DSTATE_SF_pack)(NULL, &pipeline->gen7.sf, &sf);
 }
 
 static void
@@ -85,7 +85,7 @@ gen7_emit_ds_state(struct anv_pipeline *pipeline,
       return;
    }
 
-   struct GEN7_DEPTH_STENCIL_STATE state = {
+   struct GENX(DEPTH_STENCIL_STATE) state = {
       .DepthTestEnable = info->depthTestEnable,
       .DepthBufferWriteEnable = info->depthWriteEnable,
       .DepthTestFunction = vk_to_gen_compare_op[info->depthCompareOp],
@@ -103,7 +103,7 @@ gen7_emit_ds_state(struct anv_pipeline *pipeline,
       .BackFaceStencilTestFunction = vk_to_gen_compare_op[info->back.compareOp],
    };
 
-   GEN7_DEPTH_STENCIL_STATE_pack(NULL, &pipeline->gen7.depth_stencil_state, &state);
+   GENX(DEPTH_STENCIL_STATE_pack)(NULL, &pipeline->gen7.depth_stencil_state, &state);
 }
 
 static void
@@ -116,7 +116,7 @@ gen7_emit_cb_state(struct anv_pipeline *pipeline,
    if (info == NULL || info->attachmentCount == 0) {
       pipeline->blend_state =
          anv_state_pool_emit(&device->dynamic_state_pool,
-            GEN7_BLEND_STATE, 64,
+            GENX(BLEND_STATE), 64,
             .ColorBufferBlendEnable = false,
             .WriteDisableAlpha = true,
             .WriteDisableRed = true,
@@ -129,7 +129,7 @@ gen7_emit_cb_state(struct anv_pipeline *pipeline,
       const VkPipelineColorBlendAttachmentState *a = &info->pAttachments[0];
       pipeline->blend_state =
          anv_state_pool_emit(&device->dynamic_state_pool,
-            GEN7_BLEND_STATE, 64,
+            GENX(BLEND_STATE), 64,
 
             .ColorBufferBlendEnable = a->blendEnable,
             .IndependentAlphaBlendEnable = true, /* FIXME: yes? */
@@ -169,11 +169,11 @@ gen7_emit_cb_state(struct anv_pipeline *pipeline,
             );
     }
 
-   anv_batch_emit(&pipeline->batch, GEN7_3DSTATE_BLEND_STATE_POINTERS,
+   anv_batch_emit(&pipeline->batch, GENX(3DSTATE_BLEND_STATE_POINTERS),
                   .BlendStatePointer = pipeline->blend_state.offset);
 }
 
-GENX_FUNC(GEN7, GEN75) VkResult
+VkResult
 genX(graphics_pipeline_create)(
     VkDevice                                    _device,
     struct anv_pipeline_cache *                 cache,
@@ -216,7 +216,7 @@ genX(graphics_pipeline_create)(
    const VkPipelineRasterizationStateCreateInfo *rs_info =
       pCreateInfo->pRasterizationState;
 
-   anv_batch_emit(&pipeline->batch, GEN7_3DSTATE_CLIP,
+   anv_batch_emit(&pipeline->batch, GENX(3DSTATE_CLIP),
       .FrontWinding                             = vk_to_gen_front_face[rs_info->frontFace],
       .CullMode                                 = vk_to_gen_cullmode[rs_info->cullMode],
       .ClipEnable                               = true,
@@ -237,11 +237,11 @@ genX(graphics_pipeline_create)(
    uint32_t samples = 1;
    uint32_t log2_samples = __builtin_ffs(samples) - 1;
 
-   anv_batch_emit(&pipeline->batch, GEN7_3DSTATE_MULTISAMPLE,
+   anv_batch_emit(&pipeline->batch, GENX(3DSTATE_MULTISAMPLE),
       .PixelLocation                            = PIXLOC_CENTER,
       .NumberofMultisamples                     = log2_samples);
 
-   anv_batch_emit(&pipeline->batch, GEN7_3DSTATE_SAMPLE_MASK,
+   anv_batch_emit(&pipeline->batch, GENX(3DSTATE_SAMPLE_MASK),
       .SampleMask                               = 0xff);
 
    const struct brw_vue_prog_data *vue_prog_data = &pipeline->vs_prog_data.base;
@@ -314,7 +314,7 @@ genX(graphics_pipeline_create)(
          .DispatchMode                          = gs_prog_data->base.dispatch_mode,
          .GSStatisticsEnable                    = true,
          .IncludePrimitiveID                    = gs_prog_data->include_primitive_id,
-#     if (ANV_IS_HASWELL)
+#     if (GEN_IS_HASWELL)
          .ReorderMode                           = REORDER_TRAILING,
 #     else
          .ReorderEnable                         = true,
@@ -326,10 +326,10 @@ genX(graphics_pipeline_create)(
      anv_finishme("disabling ps");
 
      /* FIXME: generated header doesn't emit attr swizzle fields */
-     anv_batch_emit(&pipeline->batch, GEN7_3DSTATE_SBE);
+     anv_batch_emit(&pipeline->batch, GENX(3DSTATE_SBE));
 
      /* FIXME-GEN7: This needs a lot more work, cf gen7 upload_wm_state(). */
-     anv_batch_emit(&pipeline->batch, GEN7_3DSTATE_WM,
+     anv_batch_emit(&pipeline->batch, GENX(3DSTATE_WM),
 		    .StatisticsEnable                         = true,
 		    .ThreadDispatchEnable                     = false,
 		    .LineEndCapAntialiasingRegionWidth        = 0, /* 0.5 pixels */
@@ -349,7 +349,7 @@ genX(graphics_pipeline_create)(
          anv_finishme("primitive_id needs sbe swizzling setup");
 
       /* FIXME: generated header doesn't emit attr swizzle fields */
-      anv_batch_emit(&pipeline->batch, GEN7_3DSTATE_SBE,
+      anv_batch_emit(&pipeline->batch, GENX(3DSTATE_SBE),
                      .NumberofSFOutputAttributes               = pipeline->wm_prog_data.num_varying_inputs,
                      .VertexURBEntryReadLength                 = urb_length,
                      .VertexURBEntryReadOffset                 = urb_offset,
@@ -390,7 +390,7 @@ genX(graphics_pipeline_create)(
                      .KernelStartPointer2                      = pipeline->ps_ksp2);
 
       /* FIXME-GEN7: This needs a lot more work, cf gen7 upload_wm_state(). */
-      anv_batch_emit(&pipeline->batch, GEN7_3DSTATE_WM,
+      anv_batch_emit(&pipeline->batch, GENX(3DSTATE_WM),
                      .StatisticsEnable                         = true,
                      .ThreadDispatchEnable                     = true,
                      .LineEndCapAntialiasingRegionWidth        = 0, /* 0.5 pixels */
diff --git a/src/intel/vulkan/gen7_state.c b/src/intel/vulkan/gen7_state.c
index 77bdb75260c..5323c378d02 100644
--- a/src/intel/vulkan/gen7_state.c
+++ b/src/intel/vulkan/gen7_state.c
@@ -29,8 +29,8 @@
 
 #include "anv_private.h"
 
-#include "genxml/gen7_pack.h"
-#include "genxml/gen75_pack.h"
+#include "genxml/gen_macros.h"
+#include "genxml/genX_pack.h"
 
 #include "genX_state_util.h"
 
@@ -43,7 +43,7 @@ genX(init_device_state)(struct anv_device *device)
    batch.start = batch.next = cmds;
    batch.end = (void *) cmds + sizeof(cmds);
 
-   anv_batch_emit(&batch, GEN7_PIPELINE_SELECT,
+   anv_batch_emit(&batch, GENX(PIPELINE_SELECT),
                   .PipelineSelection = _3D);
 
    anv_batch_emit(&batch, GENX(3DSTATE_VF_STATISTICS),
@@ -52,7 +52,7 @@ genX(init_device_state)(struct anv_device *device)
    anv_batch_emit(&batch, GENX(3DSTATE_TE), .TEEnable = false);
    anv_batch_emit(&batch, GENX(3DSTATE_DS), .DSFunctionEnable = false);
    anv_batch_emit(&batch, GENX(3DSTATE_STREAMOUT), .SOFunctionEnable = false);
-   anv_batch_emit(&batch, GEN7_3DSTATE_AA_LINE_PARAMETERS);
+   anv_batch_emit(&batch, GENX(3DSTATE_AA_LINE_PARAMETERS));
    anv_batch_emit(&batch, GENX(MI_BATCH_BUFFER_END));
 
    assert(batch.next <= batch.end);
@@ -60,7 +60,7 @@ genX(init_device_state)(struct anv_device *device)
    return anv_device_submit_simple_batch(device, &batch);
 }
 
-GENX_FUNC(GEN7, GEN75) void
+void
 genX(fill_buffer_surface_state)(void *state, enum isl_format format,
                                 uint32_t offset, uint32_t range,
                                 uint32_t stride)
@@ -79,7 +79,7 @@ genX(fill_buffer_surface_state)(void *state, enum isl_format format,
       .Width                                    = (num_elements - 1) & 0x7f,
       .Depth                                    = ((num_elements - 1) >> 21) & 0x3f,
       .SurfacePitch                             = stride - 1,
-#  if (ANV_IS_HASWELL)
+#  if (GEN_IS_HASWELL)
       .ShaderChannelSelectRed                   = SCS_RED,
       .ShaderChannelSelectGreen                 = SCS_GREEN,
       .ShaderChannelSelectBlue                  = SCS_BLUE,
@@ -107,7 +107,7 @@ VkResult genX(CreateSampler)(
    if (!sampler)
       return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
 
-   struct GEN7_SAMPLER_STATE sampler_state = {
+   struct GENX(SAMPLER_STATE) sampler_state = {
       .SamplerDisable = false,
       .TextureBorderColorMode = DX10OGL,
       .LODPreClampEnable = CLAMP_ENABLE_OGL,
@@ -145,7 +145,7 @@ VkResult genX(CreateSampler)(
       .TCZAddressControlMode = vk_to_gen_tex_address[pCreateInfo->addressModeW],
    };
 
-   GEN7_SAMPLER_STATE_pack(NULL, sampler->state, &sampler_state);
+   GENX(SAMPLER_STATE_pack)(NULL, sampler->state, &sampler_state);
 
    *pSampler = anv_sampler_to_handle(sampler);
 
@@ -227,7 +227,7 @@ genX(fill_image_surface_state)(struct anv_device *device, void *state_map,
       .SurfaceMinLOD = 0, /* TEMPLATE */
 
       .MCSEnable = false,
-#  if (ANV_IS_HASWELL)
+#  if (GEN_IS_HASWELL)
       .ShaderChannelSelectRed = vk_to_gen_swizzle[iview->swizzle.r],
       .ShaderChannelSelectGreen = vk_to_gen_swizzle[iview->swizzle.g],
       .ShaderChannelSelectBlue = vk_to_gen_swizzle[iview->swizzle.b],
diff --git a/src/intel/vulkan/gen8_cmd_buffer.c b/src/intel/vulkan/gen8_cmd_buffer.c
index b741612c891..3221f5e2dc4 100644
--- a/src/intel/vulkan/gen8_cmd_buffer.c
+++ b/src/intel/vulkan/gen8_cmd_buffer.c
@@ -29,8 +29,8 @@
 
 #include "anv_private.h"
 
-#include "genxml/gen8_pack.h"
-#include "genxml/gen9_pack.h"
+#include "genxml/gen_macros.h"
+#include "genxml/genX_pack.h"
 
 static uint32_t
 cmd_buffer_flush_push_constants(struct anv_cmd_buffer *cmd_buffer)
@@ -70,7 +70,7 @@ cmd_buffer_flush_push_constants(struct anv_cmd_buffer *cmd_buffer)
    return flushed;
 }
 
-#if ANV_GEN == 8
+#if GEN_GEN == 8
 static void
 emit_viewport_state(struct anv_cmd_buffer *cmd_buffer,
                     uint32_t count, const VkViewport *viewports)
@@ -213,6 +213,8 @@ __emit_genx_sf_state(struct anv_cmd_buffer *cmd_buffer)
       anv_batch_emit_merge(&cmd_buffer->batch, sf_dw,
                            cmd_buffer->state.pipeline->gen8.sf);
 }
+
+#include "genxml/gen9_pack.h"
 static void
 __emit_gen9_sf_state(struct anv_cmd_buffer *cmd_buffer)
 {
@@ -339,14 +341,14 @@ genX(cmd_buffer_flush_state)(struct anv_cmd_buffer *cmd_buffer)
     * across different state packets for gen8 and gen9. We handle that by
     * using a big old #if switch here.
     */
-#if ANV_GEN == 8
+#if GEN_GEN == 8
    if (cmd_buffer->state.dirty & (ANV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS |
                                   ANV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE)) {
       struct anv_state cc_state =
          anv_cmd_buffer_alloc_dynamic_state(cmd_buffer,
-                                            GEN8_COLOR_CALC_STATE_length * 4,
+                                            GENX(COLOR_CALC_STATE_length) * 4,
                                             64);
-      struct GEN8_COLOR_CALC_STATE cc = {
+      struct GENX(COLOR_CALC_STATE) cc = {
          .BlendConstantColorRed = cmd_buffer->state.dynamic.blend_constants[0],
          .BlendConstantColorGreen = cmd_buffer->state.dynamic.blend_constants[1],
          .BlendConstantColorBlue = cmd_buffer->state.dynamic.blend_constants[2],
@@ -356,13 +358,13 @@ genX(cmd_buffer_flush_state)(struct anv_cmd_buffer *cmd_buffer)
          .BackFaceStencilReferenceValue =
             cmd_buffer->state.dynamic.stencil_reference.back,
       };
-      GEN8_COLOR_CALC_STATE_pack(NULL, cc_state.map, &cc);
+      GENX(COLOR_CALC_STATE_pack)(NULL, cc_state.map, &cc);
 
       if (!cmd_buffer->device->info.has_llc)
          anv_state_clflush(cc_state);
 
       anv_batch_emit(&cmd_buffer->batch,
-                     GEN8_3DSTATE_CC_STATE_POINTERS,
+                     GENX(3DSTATE_CC_STATE_POINTERS),
                      .ColorCalcStatePointer = cc_state.offset,
                      .ColorCalcStatePointerValid = true);
    }
@@ -370,10 +372,10 @@ genX(cmd_buffer_flush_state)(struct anv_cmd_buffer *cmd_buffer)
    if (cmd_buffer->state.dirty & (ANV_CMD_DIRTY_PIPELINE |
                                   ANV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK |
                                   ANV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK)) {
-      uint32_t wm_depth_stencil_dw[GEN8_3DSTATE_WM_DEPTH_STENCIL_length];
+      uint32_t wm_depth_stencil_dw[GENX(3DSTATE_WM_DEPTH_STENCIL_length)];
 
-      struct GEN8_3DSTATE_WM_DEPTH_STENCIL wm_depth_stencil = {
-         GEN8_3DSTATE_WM_DEPTH_STENCIL_header,
+      struct GENX(3DSTATE_WM_DEPTH_STENCIL wm_depth_stencil) = {
+         GENX(3DSTATE_WM_DEPTH_STENCIL_header),
 
          /* Is this what we need to do? */
          .StencilBufferWriteEnable =
@@ -389,8 +391,8 @@ genX(cmd_buffer_flush_state)(struct anv_cmd_buffer *cmd_buffer)
          .BackfaceStencilWriteMask =
             cmd_buffer->state.dynamic.stencil_write_mask.back & 0xff,
       };
-      GEN8_3DSTATE_WM_DEPTH_STENCIL_pack(NULL, wm_depth_stencil_dw,
-                                         &wm_depth_stencil);
+      GENX(3DSTATE_WM_DEPTH_STENCIL_pack)(NULL, wm_depth_stencil_dw,
+                                          &wm_depth_stencil);
 
       anv_batch_emit_merge(&cmd_buffer->batch, wm_depth_stencil_dw,
                            pipeline->gen8.wm_depth_stencil);
@@ -568,7 +570,7 @@ genX(cmd_buffer_flush_compute_state)(struct anv_cmd_buffer *cmd_buffer)
    config_l3(cmd_buffer, needs_slm);
 
    if (cmd_buffer->state.current_pipeline != GPGPU) {
-#if ANV_GEN < 10
+#if GEN_GEN < 10
       /* From the Broadwell PRM, Volume 2a: Instructions, PIPELINE_SELECT:
        *
        *   Software must clear the COLOR_CALC_STATE Valid field in
@@ -583,7 +585,7 @@ genX(cmd_buffer_flush_compute_state)(struct anv_cmd_buffer *cmd_buffer)
 #endif
 
       anv_batch_emit(&cmd_buffer->batch, GENX(PIPELINE_SELECT),
-#if ANV_GEN >= 9
+#if GEN_GEN >= 9
                      .MaskBits = 3,
 #endif
                      .PipelineSelection = GPGPU);
diff --git a/src/intel/vulkan/gen8_pipeline.c b/src/intel/vulkan/gen8_pipeline.c
index f0411562fba..dc15e2066c5 100644
--- a/src/intel/vulkan/gen8_pipeline.c
+++ b/src/intel/vulkan/gen8_pipeline.c
@@ -29,8 +29,8 @@
 
 #include "anv_private.h"
 
-#include "genxml/gen8_pack.h"
-#include "genxml/gen9_pack.h"
+#include "genxml/gen_macros.h"
+#include "genxml/genX_pack.h"
 
 #include "genX_pipeline_util.h"
 
@@ -83,7 +83,7 @@ emit_rs_state(struct anv_pipeline *pipeline,
       .FrontFaceFillMode = vk_to_gen_fillmode[info->polygonMode],
       .BackFaceFillMode = vk_to_gen_fillmode[info->polygonMode],
       .ScissorRectangleEnable = !(extra && extra->disable_scissor),
-#if ANV_GEN == 8
+#if GEN_GEN == 8
       .ViewportZClipTestEnable = true,
 #else
       /* GEN9+ splits ViewportZClipTestEnable into near and far enable bits */
@@ -178,7 +178,7 @@ static void
 emit_ds_state(struct anv_pipeline *pipeline,
               const VkPipelineDepthStencilStateCreateInfo *info)
 {
-   uint32_t *dw = ANV_GEN == 8 ?
+   uint32_t *dw = GEN_GEN == 8 ?
       pipeline->gen8.wm_depth_stencil : pipeline->gen9.wm_depth_stencil;
 
    if (info == NULL) {
@@ -414,7 +414,7 @@ genX(graphics_pipeline_create)(
 
    const struct brw_wm_prog_data *wm_prog_data = &pipeline->wm_prog_data;
 
-   const int num_thread_bias = ANV_GEN == 8 ? 2 : 1;
+   const int num_thread_bias = GEN_GEN == 8 ? 2 : 1;
    if (pipeline->ps_ksp0 == NO_KERNEL) {
       anv_batch_emit(&pipeline->batch, GENX(3DSTATE_PS));
       anv_batch_emit(&pipeline->batch, GENX(3DSTATE_PS_EXTRA),
@@ -477,7 +477,7 @@ genX(graphics_pipeline_create)(
                      .NumberofSFOutputAttributes =
                      wm_prog_data->num_varying_inputs,
 
-#if ANV_GEN >= 9
+#if GEN_GEN >= 9
                      .Attribute0ActiveComponentFormat = ACF_XYZW,
                      .Attribute1ActiveComponentFormat = ACF_XYZW,
                      .Attribute2ActiveComponentFormat = ACF_XYZW,
@@ -556,7 +556,7 @@ genX(graphics_pipeline_create)(
                      .PixelShaderIsPerSample = per_sample_ps,
                      .PixelShaderUsesSourceDepth = wm_prog_data->uses_src_depth,
                      .PixelShaderUsesSourceW = wm_prog_data->uses_src_w,
-#if ANV_GEN >= 9
+#if GEN_GEN >= 9
                      .PixelShaderPullsBary = wm_prog_data->pulls_bary,
                      .InputCoverageMaskState = wm_prog_data->uses_sample_mask ?
                         ICMS_INNER_CONSERVATIVE : ICMS_NONE,
diff --git a/src/intel/vulkan/gen8_state.c b/src/intel/vulkan/gen8_state.c
index 04cfff5444d..fdde705f0d6 100644
--- a/src/intel/vulkan/gen8_state.c
+++ b/src/intel/vulkan/gen8_state.c
@@ -29,8 +29,8 @@
 
 #include "anv_private.h"
 
-#include "genxml/gen8_pack.h"
-#include "genxml/gen9_pack.h"
+#include "genxml/gen_macros.h"
+#include "genxml/genX_pack.h"
 
 #include "genX_state_util.h"
 
diff --git a/src/intel/vulkan/genX_cmd_buffer.c b/src/intel/vulkan/genX_cmd_buffer.c
index 5498d1d68c6..9be87a3ff05 100644
--- a/src/intel/vulkan/genX_cmd_buffer.c
+++ b/src/intel/vulkan/genX_cmd_buffer.c
@@ -26,15 +26,8 @@
 
 #include "anv_private.h"
 
-#if (ANV_GEN == 9)
-#  include "genxml/gen9_pack.h"
-#elif (ANV_GEN == 8)
-#  include "genxml/gen8_pack.h"
-#elif (ANV_IS_HASWELL)
-#  include "genxml/gen75_pack.h"
-#elif (ANV_GEN == 7)
-#  include "genxml/gen7_pack.h"
-#endif
+#include "genxml/gen_macros.h"
+#include "genxml/genX_pack.h"
 
 void
 genX(cmd_buffer_emit_state_base_address)(struct anv_cmd_buffer *cmd_buffer)
@@ -48,7 +41,7 @@ genX(cmd_buffer_emit_state_base_address)(struct anv_cmd_buffer *cmd_buffer)
       scratch_bo = &device->scratch_block_pool.bo;
 
 /* XXX: Do we need this on more than just BDW? */
-#if (ANV_GEN >= 8)
+#if (GEN_GEN >= 8)
    /* Emit a render target cache flush.
     *
     * This isn't documented anywhere in the PRM.  However, it seems to be
@@ -81,7 +74,7 @@ genX(cmd_buffer_emit_state_base_address)(struct anv_cmd_buffer *cmd_buffer)
       .InstructionMemoryObjectControlState = GENX(MOCS),
       .InstructionBaseAddressModifyEnable = true,
 
-#  if (ANV_GEN >= 8)
+#  if (GEN_GEN >= 8)
       /* Broadwell requires that we specify a buffer size for a bunch of
        * these fields.  However, since we will be growing the BO's live, we
        * just set them all to the maximum.
@@ -288,7 +281,7 @@ emit_base_vertex_instance_bo(struct anv_cmd_buffer *cmd_buffer,
          .VertexBufferIndex = 32, /* Reserved for this */
          .AddressModifyEnable = true,
          .BufferPitch = 0,
-#if (ANV_GEN >= 8)
+#if (GEN_GEN >= 8)
          .MemoryObjectControlState = GENX(MOCS),
          .BufferStartingAddress = { bo, offset },
          .BufferSize = 8
@@ -543,7 +536,7 @@ genX(flush_pipeline_select_3d)(struct anv_cmd_buffer *cmd_buffer)
 {
    if (cmd_buffer->state.current_pipeline != _3D) {
       anv_batch_emit(&cmd_buffer->batch, GENX(PIPELINE_SELECT),
-#if ANV_GEN >= 9
+#if GEN_GEN >= 9
                      .MaskBits = 3,
 #endif
                      .PipelineSelection = _3D);
@@ -587,7 +580,7 @@ cmd_buffer_emit_depth_stencil(struct anv_cmd_buffer *cmd_buffer)
          .Depth = 1 - 1,
          .MinimumArrayElement = 0,
          .DepthBufferObjectControlState = GENX(MOCS),
-#if ANV_GEN >= 8
+#if GEN_GEN >= 8
          .SurfaceQPitch = isl_surf_get_array_pitch_el_rows(&image->depth_surface.isl) >> 2,
 #endif
          .RenderTargetViewExtent = 1 - 1);
@@ -620,7 +613,7 @@ cmd_buffer_emit_depth_stencil(struct anv_cmd_buffer *cmd_buffer)
    /* Emit 3DSTATE_STENCIL_BUFFER */
    if (has_stencil) {
       anv_batch_emit(&cmd_buffer->batch, GENX(3DSTATE_STENCIL_BUFFER),
-#if ANV_GEN >= 8 || ANV_IS_HASWELL
+#if GEN_GEN >= 8 || GEN_IS_HASWELL
          .StencilBufferEnable = true,
 #endif
          .StencilBufferObjectControlState = GENX(MOCS),
@@ -632,7 +625,7 @@ cmd_buffer_emit_depth_stencil(struct anv_cmd_buffer *cmd_buffer)
           */
          .SurfacePitch = 2 * image->stencil_surface.isl.row_pitch - 1,
 
-#if ANV_GEN >= 8
+#if GEN_GEN >= 8
          .SurfaceQPitch = isl_surf_get_array_pitch_el_rows(&image->stencil_surface.isl) >> 2,
 #endif
          .SurfaceBaseAddress = {
diff --git a/src/intel/vulkan/genX_pipeline.c b/src/intel/vulkan/genX_pipeline.c
index 54ec8307d02..41a5d0f889c 100644
--- a/src/intel/vulkan/genX_pipeline.c
+++ b/src/intel/vulkan/genX_pipeline.c
@@ -23,15 +23,8 @@
 
 #include "anv_private.h"
 
-#if (ANV_GEN == 9)
-#  include "genxml/gen9_pack.h"
-#elif (ANV_GEN == 8)
-#  include "genxml/gen8_pack.h"
-#elif (ANV_IS_HASWELL)
-#  include "genxml/gen75_pack.h"
-#elif (ANV_GEN == 7)
-#  include "genxml/gen7_pack.h"
-#endif
+#include "genxml/gen_macros.h"
+#include "genxml/genX_pack.h"
 
 VkResult
 genX(compute_pipeline_create)(
@@ -94,19 +87,19 @@ genX(compute_pipeline_create)(
    anv_batch_emit(&pipeline->batch, GENX(MEDIA_VFE_STATE),
                   .ScratchSpaceBasePointer = pipeline->scratch_start[MESA_SHADER_COMPUTE],
                   .PerThreadScratchSpace = ffs(cs_prog_data->base.total_scratch / 2048),
-#if ANV_GEN > 7
+#if GEN_GEN > 7
                   .ScratchSpaceBasePointerHigh = 0,
                   .StackSize = 0,
 #else
                   .GPGPUMode = true,
 #endif
                   .MaximumNumberofThreads = device->info.max_cs_threads - 1,
-                  .NumberofURBEntries = ANV_GEN <= 7 ? 0 : 2,
+                  .NumberofURBEntries = GEN_GEN <= 7 ? 0 : 2,
                   .ResetGatewayTimer = true,
-#if ANV_GEN <= 8
+#if GEN_GEN <= 8
                   .BypassGatewayControl = true,
 #endif
-                  .URBEntryAllocationSize = ANV_GEN <= 7 ? 0 : 2,
+                  .URBEntryAllocationSize = GEN_GEN <= 7 ? 0 : 2,
                   .CURBEAllocationSize = 0);
 
    struct brw_cs_prog_data *prog_data = &pipeline->cs_prog_data;
diff --git a/src/intel/vulkan/genX_pipeline_util.h b/src/intel/vulkan/genX_pipeline_util.h
index 696e2be7c3f..51fbd8bf273 100644
--- a/src/intel/vulkan/genX_pipeline_util.h
+++ b/src/intel/vulkan/genX_pipeline_util.h
@@ -68,7 +68,7 @@ emit_vertex_input(struct anv_pipeline *pipeline,
       elements = inputs_read >> VERT_ATTRIB_GENERIC0;
    }
 
-#if ANV_GEN >= 8
+#if GEN_GEN >= 8
    /* On BDW+, we only need to allocate space for base ids.  Setting up
     * the actual vertex and instance id is a separate packet.
     */
@@ -123,7 +123,7 @@ emit_vertex_input(struct anv_pipeline *pipeline,
       };
       GENX(VERTEX_ELEMENT_STATE_pack)(NULL, &p[1 + slot * 2], &element);
 
-#if ANV_GEN >= 8
+#if GEN_GEN >= 8
       /* On Broadwell and later, we have a separate VF_INSTANCING packet
        * that controls instancing.  On Haswell and prior, that's part of
        * VERTEX_BUFFER_STATE which we emit later.
@@ -158,7 +158,7 @@ emit_vertex_input(struct anv_pipeline *pipeline,
          .SourceElementFormat = ISL_FORMAT_R32G32_UINT,
          .Component0Control = base_ctrl,
          .Component1Control = base_ctrl,
-#if ANV_GEN >= 8
+#if GEN_GEN >= 8
          .Component2Control = VFCOMP_STORE_0,
          .Component3Control = VFCOMP_STORE_0,
 #else
@@ -169,7 +169,7 @@ emit_vertex_input(struct anv_pipeline *pipeline,
       GENX(VERTEX_ELEMENT_STATE_pack)(NULL, &p[1 + id_slot * 2], &element);
    }
 
-#if ANV_GEN >= 8
+#if GEN_GEN >= 8
    anv_batch_emit(&pipeline->batch, GENX(3DSTATE_VF_SGVS),
                   .VertexIDEnable = pipeline->vs_prog_data.uses_vertexid,
                   .VertexIDComponentNumber = 2,
@@ -183,7 +183,7 @@ emit_vertex_input(struct anv_pipeline *pipeline,
 static inline void
 emit_urb_setup(struct anv_pipeline *pipeline)
 {
-#if ANV_GEN == 7
+#if GEN_GEN == 7 && !GEN_IS_HASWELL
    struct anv_device *device = pipeline->device;
 
    /* From the IVB PRM Vol. 2, Part 1, Section 3.2.1:
diff --git a/src/intel/vulkan/genX_state_util.h b/src/intel/vulkan/genX_state_util.h
index 67f798ab66e..10b3a9f42c5 100644
--- a/src/intel/vulkan/genX_state_util.h
+++ b/src/intel/vulkan/genX_state_util.h
@@ -57,7 +57,7 @@ anv_surface_format(const struct anv_device *device, enum isl_format format,
    }
 }
 
-#if ANV_GEN > 7 || ANV_IS_HASWELL
+#if GEN_GEN > 7 || GEN_IS_HASWELL
 static const uint32_t vk_to_gen_swizzle[] = {
    [VK_COMPONENT_SWIZZLE_ZERO]                 = SCS_ZERO,
    [VK_COMPONENT_SWIZZLE_ONE]                  = SCS_ONE,