diff options
| author | Jordan Justen <[email protected]> | 2020-06-12 03:02:02 -0700 |
|---|---|---|
| committer | Jordan Justen <[email protected]> | 2020-06-22 11:41:59 -0700 |
| commit | 633dec7163e83943c6744909d8a4b67aafd2eaa6 (patch) | |
| tree | 98e200f7d81bca4b117a5f4563a94188de75f301 /src/intel/vulkan | |
| parent | e2e0521ecbbc0e666582162c2bf149f1e41c73e2 (diff) | |
anv: Set L3 full way allocation at context init if L3 cfg is NULL
If the platform's default L3 config is NULL, then it now gets
initialized only at context init time, and cmd_buffer_config_l3 will
always return immediately.
Rework:
* Remove unneeded check on !cfg in cmd_buffer_config_l3 (Jason)
Signed-off-by: Jordan Justen <[email protected]>
Reviewed-by: Lionel Landwerlin <[email protected]>
Reviewed-by: Jason Ekstrand <[email protected]>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4956>
Diffstat (limited to 'src/intel/vulkan')
| -rw-r--r-- | src/intel/vulkan/genX_cmd_buffer.c | 2 | ||||
| -rw-r--r-- | src/intel/vulkan/genX_state.c | 14 |
2 files changed, 15 insertions, 1 deletions
diff --git a/src/intel/vulkan/genX_cmd_buffer.c b/src/intel/vulkan/genX_cmd_buffer.c index bf2a5a6dc75..856ae2abf11 100644 --- a/src/intel/vulkan/genX_cmd_buffer.c +++ b/src/intel/vulkan/genX_cmd_buffer.c @@ -1804,7 +1804,7 @@ void genX(cmd_buffer_config_l3)(struct anv_cmd_buffer *cmd_buffer, const struct gen_l3_config *cfg) { - assert(cfg); + assert(cfg || GEN_GEN >= 12); if (cfg == cmd_buffer->state.current_l3_config) return; diff --git a/src/intel/vulkan/genX_state.c b/src/intel/vulkan/genX_state.c index 3c5033459d0..316a56ab730 100644 --- a/src/intel/vulkan/genX_state.c +++ b/src/intel/vulkan/genX_state.c @@ -294,6 +294,20 @@ genX(init_device_state)(struct anv_device *device) #endif } +#if GEN_GEN >= 12 + const struct gen_l3_config *cfg = gen_get_default_l3_config(&device->info); + if (!cfg) { + /* Platforms with no configs just setup full-way allocation. */ + uint32_t l3cr; + anv_pack_struct(&l3cr, GENX(L3ALLOC), + .L3FullWayAllocationEnable = true); + anv_batch_emit(&batch, GENX(MI_LOAD_REGISTER_IMM), lri) { + lri.RegisterOffset = GENX(L3ALLOC_num); + lri.DataDWord = l3cr; + } + } +#endif + anv_batch_emit(&batch, GENX(MI_BATCH_BUFFER_END), bbe); assert(batch.next <= batch.end); |