diff options
| author | Anuj Phogat <[email protected]> | 2018-08-17 16:42:23 -0700 |
|---|---|---|
| committer | Anuj Phogat <[email protected]> | 2018-08-21 12:50:05 -0700 |
| commit | 2383ddace12c3f5c23d8cc20a7768b0a6cb915f6 (patch) | |
| tree | 21d03e04ce0de999a15da08752c1fc364dc657cc /src/intel/vulkan/genX_state.c | |
| parent | 81b74b5d96bce37d586525bce9181592626bf781 (diff) | |
anv/icl: Allow headerless sampler messages for pre-emptable contexts
It fixes simulator warnings in vulkancts tests complaining about missing
support for headerless sampler messages for pre-emptable contexts.
Bit 5 in SAMPLER MODE register is newly introduced for ICLLP.
Signed-off-by: Anuj Phogat <[email protected]>
Reviewed-by: Kenneth Graunke <[email protected]>
Diffstat (limited to 'src/intel/vulkan/genX_state.c')
| -rw-r--r-- | src/intel/vulkan/genX_state.c | 17 |
1 files changed, 17 insertions, 0 deletions
diff --git a/src/intel/vulkan/genX_state.c b/src/intel/vulkan/genX_state.c index b1014d9e797..d6ccd21524c 100644 --- a/src/intel/vulkan/genX_state.c +++ b/src/intel/vulkan/genX_state.c @@ -157,6 +157,23 @@ genX(init_device_state)(struct anv_device *device) gen10_emit_wa_lri_to_cache_mode_zero(&batch); #endif +#if GEN_GEN == 11 + /* The default behavior of bit 5 "Headerless Message for Pre-emptable + * Contexts" in SAMPLER MODE register is set to 0, which means + * headerless sampler messages are not allowed for pre-emptable + * contexts. Set the bit 5 to 1 to allow them. + */ + uint32_t sampler_mode; + anv_pack_struct(&sampler_mode, GENX(SAMPLER_MODE), + .HeaderlessMessageforPreemptableContexts = true, + .HeaderlessMessageforPreemptableContextsMask = true); + + anv_batch_emit(&batch, GENX(MI_LOAD_REGISTER_IMM), lri) { + lri.RegisterOffset = GENX(SAMPLER_MODE_num); + lri.DataDWord = sampler_mode; + } +#endif + /* Set the "CONSTANT_BUFFER Address Offset Disable" bit, so * 3DSTATE_CONSTANT_XS buffer 0 is an absolute address. * |