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authorLionel Landwerlin <[email protected]>2019-04-18 12:00:19 +0100
committerLionel Landwerlin <[email protected]>2019-04-18 17:43:08 +0100
commitdb5b372bb9f5a0dfea86618f8f9832f25d9eaf71 (patch)
tree8654312a556d8effde86ae7037a8bbe08fa172f2 /src/intel/vulkan/genX_state.c
parenteaadb62c9ea98f841d7ffc26c14341abdf84d2d6 (diff)
anv: implement WaEnableStateCacheRedirectToCS
This 3d performance workaround was initially put in the kernel but the media driver requires different settings so the register has been whitelisted in i915 [1] and userspace drivers are left initializing it as they wish. [1] : https://patchwork.freedesktop.org/series/59494/ Signed-off-by: Lionel Landwerlin <[email protected]> Reviewed-by: Anuj Phogat <[email protected]>
Diffstat (limited to 'src/intel/vulkan/genX_state.c')
-rw-r--r--src/intel/vulkan/genX_state.c11
1 files changed, 11 insertions, 0 deletions
diff --git a/src/intel/vulkan/genX_state.c b/src/intel/vulkan/genX_state.c
index 6d55e5dc5c6..283cd8c501a 100644
--- a/src/intel/vulkan/genX_state.c
+++ b/src/intel/vulkan/genX_state.c
@@ -212,6 +212,17 @@ genX(init_device_state)(struct anv_device *device)
lri.DataDWord = common_slice_chicken3;
}
+ /* WaEnableStateCacheRedirectToCS:icl */
+ uint32_t slice_common_eco_chicken1;
+ anv_pack_struct(&slice_common_eco_chicken1,
+ GENX(SLICE_COMMON_ECO_CHICKEN1),
+ .StateCacheRedirectToCSSectionEnable = true,
+ .StateCacheRedirectToCSSectionEnableMask = true);
+
+ anv_batch_emit(&batch, GENX(MI_LOAD_REGISTER_IMM), lri) {
+ lri.RegisterOffset = GENX(SLICE_COMMON_ECO_CHICKEN1_num);
+ lri.DataDWord = slice_common_eco_chicken1;
+ }
#endif
/* Set the "CONSTANT_BUFFER Address Offset Disable" bit, so