diff options
author | Jason Ekstrand <[email protected]> | 2016-04-18 17:03:00 -0700 |
---|---|---|
committer | Jason Ekstrand <[email protected]> | 2016-04-20 14:54:09 -0700 |
commit | 50018522d2f2e1deb91710d63e0985c0b3dc8818 (patch) | |
tree | 439040b1a4945376f9eed1b65d70ade5ccf2a177 /src/intel/vulkan/genX_pipeline_util.h | |
parent | 0a45395902134a4541be68c0522dbb623f32f765 (diff) |
anv: s/anv_batch_emit_blk/anv_batch_emit/
Acked-by: Kristian Høgsberg <[email protected]>
Diffstat (limited to 'src/intel/vulkan/genX_pipeline_util.h')
-rw-r--r-- | src/intel/vulkan/genX_pipeline_util.h | 12 |
1 files changed, 6 insertions, 6 deletions
diff --git a/src/intel/vulkan/genX_pipeline_util.h b/src/intel/vulkan/genX_pipeline_util.h index 46be36d4b77..fe1f8120c4b 100644 --- a/src/intel/vulkan/genX_pipeline_util.h +++ b/src/intel/vulkan/genX_pipeline_util.h @@ -130,7 +130,7 @@ emit_vertex_input(struct anv_pipeline *pipeline, * that controls instancing. On Haswell and prior, that's part of * VERTEX_BUFFER_STATE which we emit later. */ - anv_batch_emit_blk(&pipeline->batch, GENX(3DSTATE_VF_INSTANCING), vfi) { + anv_batch_emit(&pipeline->batch, GENX(3DSTATE_VF_INSTANCING), vfi) { vfi.InstancingEnable = pipeline->instancing_enable[desc->binding], vfi.VertexElementIndex = slot, /* Vulkan so far doesn't have an instance divisor, so @@ -173,7 +173,7 @@ emit_vertex_input(struct anv_pipeline *pipeline, } #if GEN_GEN >= 8 - anv_batch_emit_blk(&pipeline->batch, GENX(3DSTATE_VF_SGVS), sgvs) { + anv_batch_emit(&pipeline->batch, GENX(3DSTATE_VF_SGVS), sgvs) { sgvs.VertexIDEnable = vs_prog_data->uses_vertexid; sgvs.VertexIDComponentNumber = 2; sgvs.VertexIDElementOffset = id_slot; @@ -198,7 +198,7 @@ emit_urb_setup(struct anv_pipeline *pipeline) * 3DSTATE_SAMPLER_STATE_POINTER_VS command. Only one PIPE_CONTROL * needs to be sent before any combination of VS associated 3DSTATE." */ - anv_batch_emit_blk(&pipeline->batch, GEN7_PIPE_CONTROL, pc) { + anv_batch_emit(&pipeline->batch, GEN7_PIPE_CONTROL, pc) { pc.DepthStallEnable = true; pc.PostSyncOperation = WriteImmediateData; pc.Address = (struct anv_address) { &device->workaround_bo, 0 }; @@ -208,8 +208,8 @@ emit_urb_setup(struct anv_pipeline *pipeline) unsigned push_start = 0; for (int i = MESA_SHADER_VERTEX; i <= MESA_SHADER_FRAGMENT; i++) { unsigned push_size = pipeline->urb.push_size[i]; - anv_batch_emit_blk(&pipeline->batch, - GENX(3DSTATE_PUSH_CONSTANT_ALLOC_VS), alloc) { + anv_batch_emit(&pipeline->batch, + GENX(3DSTATE_PUSH_CONSTANT_ALLOC_VS), alloc) { alloc._3DCommandSubOpcode = 18 + i; alloc.ConstantBufferOffset = (push_size > 0) ? push_start : 0; alloc.ConstantBufferSize = push_size; @@ -218,7 +218,7 @@ emit_urb_setup(struct anv_pipeline *pipeline) } for (int i = MESA_SHADER_VERTEX; i <= MESA_SHADER_GEOMETRY; i++) { - anv_batch_emit_blk(&pipeline->batch, GENX(3DSTATE_URB_VS), urb) { + anv_batch_emit(&pipeline->batch, GENX(3DSTATE_URB_VS), urb) { urb._3DCommandSubOpcode = 48 + i; urb.VSURBStartingAddress = pipeline->urb.start[i]; urb.VSURBEntryAllocationSize = pipeline->urb.size[i] - 1; |