anv/pipeline: Set URB offset to zero if size is zero

After 3ecd357d816dc71b2c6ebd6ace38c76ebb25674e, it may be possible for
the VS to get assigned all of the URB space.

On Ivy Bridge, this will cause the offset for the other stages to be
16, which cannot be packed into the ConstantBufferOffset field of
3DSTATE_PUSH_CONSTANT_ALLOC_*.

Instead we can set the offset to zero if the stage size is zero.

Signed-off-by: Jordan Justen <[email protected]>

1 files changed, 3 insertions, 2 deletions

diff --git a/src/intel/vulkan/genX_pipeline_util.h b/src/intel/vulkan/genX_pipeline_util.h
index cf4e0358741..d940aba67b5 100644
--- a/src/intel/vulkan/genX_pipeline_util.h
+++ b/src/intel/vulkan/genX_pipeline_util.h
@@ -202,10 +202,11 @@ emit_urb_setup(struct anv_pipeline *pipeline)
 
    unsigned push_start = 0;
    for (int i = MESA_SHADER_VERTEX; i <= MESA_SHADER_FRAGMENT; i++) {
+      unsigned push_size = pipeline->urb.push_size[i];
       anv_batch_emit(&pipeline->batch, GENX(3DSTATE_PUSH_CONSTANT_ALLOC_VS),
          ._3DCommandSubOpcode                   = 18 + i,
-         .ConstantBufferOffset                  = push_start,
-         .ConstantBufferSize                    = pipeline->urb.push_size[i]);
+         .ConstantBufferOffset                  = (push_size > 0) ? push_start : 0,
+         .ConstantBufferSize                    = push_size);
       push_start += pipeline->urb.push_size[i];
    }