diff options
author | Jason Ekstrand <[email protected]> | 2016-12-07 20:31:12 -0800 |
---|---|---|
committer | Jason Ekstrand <[email protected]> | 2017-02-14 14:18:55 -0800 |
commit | 6ce8592836b84f12bfe60de9f7913bfab11b8ef5 (patch) | |
tree | cc9155ff76eadf2be61b05731363762bff3ea952 /src/intel/vulkan/genX_pipeline.c | |
parent | 114c281e707919a1420d3a20219ce4392d8b360d (diff) |
anv: Disable stencil writes when both write masks are zero
Vulkan doesn't have a stencilWriteEnable bit like it does for depth.
Instead, you have a stencil mask. Since the stencil mask is handled as
dynamic state, we have to handle it later during command buffer
construction. This, combined with a later commit, seems to help Dota2
on my Broadwell GT3e desktop by a couple percent because it allows the
hardware to move the depth and stencil writes to early in more cases.
Reviewed-by: Lionel Landwerlin <[email protected]>
Reviewed-by: Nanley Chery <[email protected]>
Diffstat (limited to 'src/intel/vulkan/genX_pipeline.c')
-rw-r--r-- | src/intel/vulkan/genX_pipeline.c | 6 |
1 files changed, 4 insertions, 2 deletions
diff --git a/src/intel/vulkan/genX_pipeline.c b/src/intel/vulkan/genX_pipeline.c index 55d1e5571d7..f641661db1b 100644 --- a/src/intel/vulkan/genX_pipeline.c +++ b/src/intel/vulkan/genX_pipeline.c @@ -663,12 +663,15 @@ emit_ds_state(struct anv_pipeline *pipeline, /* We're going to OR this together with the dynamic state. We need * to make sure it's initialized to something useful. */ + pipeline->writes_stencil = false; memset(depth_stencil_dw, 0, sizeof(depth_stencil_dw)); return; } /* VkBool32 depthBoundsTestEnable; // optional (depth_bounds_test) */ + pipeline->writes_stencil = info->stencilTestEnable; + #if GEN_GEN <= 7 struct GENX(DEPTH_STENCIL_STATE) depth_stencil = { #else @@ -680,7 +683,6 @@ emit_ds_state(struct anv_pipeline *pipeline, .DoubleSidedStencilEnable = true, .StencilTestEnable = info->stencilTestEnable, - .StencilBufferWriteEnable = info->stencilTestEnable, .StencilFailOp = vk_to_gen_stencil_op[info->front.failOp], .StencilPassDepthPassOp = vk_to_gen_stencil_op[info->front.passOp], .StencilPassDepthFailOp = vk_to_gen_stencil_op[info->front.depthFailOp], @@ -707,7 +709,7 @@ emit_ds_state(struct anv_pipeline *pipeline, } if (!(aspects & VK_IMAGE_ASPECT_STENCIL_BIT)) { - depth_stencil.StencilBufferWriteEnable = false; + pipeline->writes_stencil = false; depth_stencil.StencilTestFunction = PREFILTEROPALWAYS; depth_stencil.BackfaceStencilTestFunction = PREFILTEROPALWAYS; } |