diff options
author | Jason Ekstrand <[email protected]> | 2017-12-15 11:39:31 -0800 |
---|---|---|
committer | Jason Ekstrand <[email protected]> | 2018-01-23 21:10:25 -0800 |
commit | 9af5379228d7be9c7ea41e0912a8770d28ead92b (patch) | |
tree | 366526d2b51b06e066ea00450ab5f30fc7fa758a /src/intel/vulkan/genX_cmd_buffer.c | |
parent | ddc2d285484a1607f79ffeb2fc6c09367c6aea1f (diff) |
anv/cmd_buffer: Add substructs to anv_cmd_state for graphics and compute
Initially, these just contain the pipeline in a base struct.
Tested-by: Józef Kucia <[email protected]>
Reviewed-by: Topi Pohjolainen <[email protected]>
Cc: "18.0" <[email protected]>
Diffstat (limited to 'src/intel/vulkan/genX_cmd_buffer.c')
-rw-r--r-- | src/intel/vulkan/genX_cmd_buffer.c | 45 |
1 files changed, 24 insertions, 21 deletions
diff --git a/src/intel/vulkan/genX_cmd_buffer.c b/src/intel/vulkan/genX_cmd_buffer.c index f00f3363bc3..389dd7871d6 100644 --- a/src/intel/vulkan/genX_cmd_buffer.c +++ b/src/intel/vulkan/genX_cmd_buffer.c @@ -1398,7 +1398,8 @@ void genX(CmdPipelineBarrier)( static void cmd_buffer_alloc_push_constants(struct anv_cmd_buffer *cmd_buffer) { - VkShaderStageFlags stages = cmd_buffer->state.pipeline->active_stages; + VkShaderStageFlags stages = + cmd_buffer->state.gfx.base.pipeline->active_stages; /* In order to avoid thrash, we assume that vertex and fragment stages * always exist. In the rare case where one is missing *and* the other @@ -1496,19 +1497,21 @@ emit_binding_table(struct anv_cmd_buffer *cmd_buffer, struct anv_state *bt_state) { struct anv_subpass *subpass = cmd_buffer->state.subpass; + struct anv_cmd_pipeline_state *pipe_state; struct anv_pipeline *pipeline; uint32_t bias, state_offset; switch (stage) { case MESA_SHADER_COMPUTE: - pipeline = cmd_buffer->state.compute_pipeline; + pipe_state = &cmd_buffer->state.compute.base; bias = 1; break; default: - pipeline = cmd_buffer->state.pipeline; + pipe_state = &cmd_buffer->state.gfx.base; bias = 0; break; } + pipeline = pipe_state->pipeline; if (!anv_pipeline_has_stage(pipeline, stage)) { *bt_state = (struct anv_state) { 0, }; @@ -1725,12 +1728,10 @@ emit_samplers(struct anv_cmd_buffer *cmd_buffer, gl_shader_stage stage, struct anv_state *state) { - struct anv_pipeline *pipeline; - - if (stage == MESA_SHADER_COMPUTE) - pipeline = cmd_buffer->state.compute_pipeline; - else - pipeline = cmd_buffer->state.pipeline; + struct anv_cmd_pipeline_state *pipe_state = + stage == MESA_SHADER_COMPUTE ? &cmd_buffer->state.compute.base : + &cmd_buffer->state.gfx.base; + struct anv_pipeline *pipeline = pipe_state->pipeline; if (!anv_pipeline_has_stage(pipeline, stage)) { *state = (struct anv_state) { 0, }; @@ -1780,8 +1781,10 @@ emit_samplers(struct anv_cmd_buffer *cmd_buffer, static uint32_t flush_descriptor_sets(struct anv_cmd_buffer *cmd_buffer) { + struct anv_pipeline *pipeline = cmd_buffer->state.gfx.base.pipeline; + VkShaderStageFlags dirty = cmd_buffer->state.descriptors_dirty & - cmd_buffer->state.pipeline->active_stages; + pipeline->active_stages; VkResult result = VK_SUCCESS; anv_foreach_stage(s, dirty) { @@ -1807,7 +1810,7 @@ flush_descriptor_sets(struct anv_cmd_buffer *cmd_buffer) genX(cmd_buffer_emit_state_base_address)(cmd_buffer); /* Re-emit all active binding tables */ - dirty |= cmd_buffer->state.pipeline->active_stages; + dirty |= pipeline->active_stages; anv_foreach_stage(s, dirty) { result = emit_samplers(cmd_buffer, s, &cmd_buffer->state.samplers[s]); if (result != VK_SUCCESS) { @@ -1876,7 +1879,7 @@ static void cmd_buffer_flush_push_constants(struct anv_cmd_buffer *cmd_buffer, VkShaderStageFlags dirty_stages) { - const struct anv_pipeline *pipeline = cmd_buffer->state.pipeline; + const struct anv_pipeline *pipeline = cmd_buffer->state.gfx.base.pipeline; static const uint32_t push_constant_opcodes[] = { [MESA_SHADER_VERTEX] = 21, @@ -2005,7 +2008,7 @@ cmd_buffer_flush_push_constants(struct anv_cmd_buffer *cmd_buffer, void genX(cmd_buffer_flush_state)(struct anv_cmd_buffer *cmd_buffer) { - struct anv_pipeline *pipeline = cmd_buffer->state.pipeline; + struct anv_pipeline *pipeline = cmd_buffer->state.gfx.base.pipeline; uint32_t *p; uint32_t vb_emit = cmd_buffer->state.vb_dirty & pipeline->vb_used; @@ -2212,7 +2215,7 @@ void genX(CmdDraw)( uint32_t firstInstance) { ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer); - struct anv_pipeline *pipeline = cmd_buffer->state.pipeline; + struct anv_pipeline *pipeline = cmd_buffer->state.gfx.base.pipeline; const struct brw_vs_prog_data *vs_prog_data = get_vs_prog_data(pipeline); if (anv_batch_has_error(&cmd_buffer->batch)) @@ -2250,7 +2253,7 @@ void genX(CmdDrawIndexed)( uint32_t firstInstance) { ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer); - struct anv_pipeline *pipeline = cmd_buffer->state.pipeline; + struct anv_pipeline *pipeline = cmd_buffer->state.gfx.base.pipeline; const struct brw_vs_prog_data *vs_prog_data = get_vs_prog_data(pipeline); if (anv_batch_has_error(&cmd_buffer->batch)) @@ -2402,7 +2405,7 @@ void genX(CmdDrawIndirect)( { ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer); ANV_FROM_HANDLE(anv_buffer, buffer, _buffer); - struct anv_pipeline *pipeline = cmd_buffer->state.pipeline; + struct anv_pipeline *pipeline = cmd_buffer->state.gfx.base.pipeline; const struct brw_vs_prog_data *vs_prog_data = get_vs_prog_data(pipeline); if (anv_batch_has_error(&cmd_buffer->batch)) @@ -2440,7 +2443,7 @@ void genX(CmdDrawIndexedIndirect)( { ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer); ANV_FROM_HANDLE(anv_buffer, buffer, _buffer); - struct anv_pipeline *pipeline = cmd_buffer->state.pipeline; + struct anv_pipeline *pipeline = cmd_buffer->state.gfx.base.pipeline; const struct brw_vs_prog_data *vs_prog_data = get_vs_prog_data(pipeline); if (anv_batch_has_error(&cmd_buffer->batch)) @@ -2473,7 +2476,7 @@ void genX(CmdDrawIndexedIndirect)( static VkResult flush_compute_descriptor_set(struct anv_cmd_buffer *cmd_buffer) { - struct anv_pipeline *pipeline = cmd_buffer->state.compute_pipeline; + struct anv_pipeline *pipeline = cmd_buffer->state.compute.base.pipeline; struct anv_state surfaces = { 0, }, samplers = { 0, }; VkResult result; @@ -2529,7 +2532,7 @@ flush_compute_descriptor_set(struct anv_cmd_buffer *cmd_buffer) void genX(cmd_buffer_flush_compute_state)(struct anv_cmd_buffer *cmd_buffer) { - struct anv_pipeline *pipeline = cmd_buffer->state.compute_pipeline; + struct anv_pipeline *pipeline = cmd_buffer->state.compute.base.pipeline; MAYBE_UNUSED VkResult result; assert(pipeline->active_stages == VK_SHADER_STAGE_COMPUTE_BIT); @@ -2606,7 +2609,7 @@ void genX(CmdDispatch)( uint32_t z) { ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer); - struct anv_pipeline *pipeline = cmd_buffer->state.compute_pipeline; + struct anv_pipeline *pipeline = cmd_buffer->state.compute.base.pipeline; const struct brw_cs_prog_data *prog_data = get_cs_prog_data(pipeline); if (anv_batch_has_error(&cmd_buffer->batch)) @@ -2653,7 +2656,7 @@ void genX(CmdDispatchIndirect)( { ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer); ANV_FROM_HANDLE(anv_buffer, buffer, _buffer); - struct anv_pipeline *pipeline = cmd_buffer->state.compute_pipeline; + struct anv_pipeline *pipeline = cmd_buffer->state.compute.base.pipeline; const struct brw_cs_prog_data *prog_data = get_cs_prog_data(pipeline); struct anv_bo *bo = buffer->bo; uint32_t bo_offset = buffer->offset + offset; |