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authorJordan Justen <[email protected]>2016-03-10 17:16:58 -0800
committerJordan Justen <[email protected]>2016-03-12 12:43:46 -0800
commit1b126305ded36f6b416ada08e29ff84faeafef99 (patch)
tree8371ec62ffa92660c5429627103931e28bfc0718 /src/intel/vulkan/genX_cmd_buffer.c
parent41af9b2e517dd0c17e519490ca915b96f6898390 (diff)
anv/genX: Add flush_pipeline_select_gpgpu
Signed-off-by: Jordan Justen <[email protected]>
Diffstat (limited to 'src/intel/vulkan/genX_cmd_buffer.c')
-rw-r--r--src/intel/vulkan/genX_cmd_buffer.c27
1 files changed, 27 insertions, 0 deletions
diff --git a/src/intel/vulkan/genX_cmd_buffer.c b/src/intel/vulkan/genX_cmd_buffer.c
index 723f6d81a39..d0a80f53e63 100644
--- a/src/intel/vulkan/genX_cmd_buffer.c
+++ b/src/intel/vulkan/genX_cmd_buffer.c
@@ -777,6 +777,33 @@ genX(flush_pipeline_select_3d)(struct anv_cmd_buffer *cmd_buffer)
}
}
+void
+genX(flush_pipeline_select_gpgpu)(struct anv_cmd_buffer *cmd_buffer)
+{
+ if (cmd_buffer->state.current_pipeline != GPGPU) {
+#if GEN_GEN >= 8 && GEN_GEN < 10
+ /* From the Broadwell PRM, Volume 2a: Instructions, PIPELINE_SELECT:
+ *
+ * Software must clear the COLOR_CALC_STATE Valid field in
+ * 3DSTATE_CC_STATE_POINTERS command prior to send a PIPELINE_SELECT
+ * with Pipeline Select set to GPGPU.
+ *
+ * The internal hardware docs recommend the same workaround for Gen9
+ * hardware too.
+ */
+ anv_batch_emit(&cmd_buffer->batch,
+ GENX(3DSTATE_CC_STATE_POINTERS));
+#endif
+
+ anv_batch_emit(&cmd_buffer->batch, GENX(PIPELINE_SELECT),
+#if GEN_GEN >= 9
+ .MaskBits = 3,
+#endif
+ .PipelineSelection = GPGPU);
+ cmd_buffer->state.current_pipeline = GPGPU;
+ }
+}
+
struct anv_state
genX(cmd_buffer_alloc_null_surface_state)(struct anv_cmd_buffer *cmd_buffer,
struct anv_framebuffer *fb)