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authorJason Ekstrand <[email protected]>2016-03-05 09:19:01 -0800
committerJason Ekstrand <[email protected]>2016-03-05 09:59:28 -0800
commit1afdfc3e6e022a4e5e9701b365c4f92554be999a (patch)
tree74a22417262a65758e11068ea9394e7bcb6590fd /src/intel/vulkan/gen8_pipeline.c
parent7c1660aa14094e40fba9f39ce194cb6238311b65 (diff)
anv/pipeline: Implement the depth compare EQUAL workaround on gen8+
Diffstat (limited to 'src/intel/vulkan/gen8_pipeline.c')
-rw-r--r--src/intel/vulkan/gen8_pipeline.c8
1 files changed, 8 insertions, 0 deletions
diff --git a/src/intel/vulkan/gen8_pipeline.c b/src/intel/vulkan/gen8_pipeline.c
index e8a067851cc..4a5e8674189 100644
--- a/src/intel/vulkan/gen8_pipeline.c
+++ b/src/intel/vulkan/gen8_pipeline.c
@@ -238,6 +238,14 @@ emit_ds_state(struct anv_pipeline *pipeline,
.BackfaceStencilTestFunction = vk_to_gen_compare_op[info->back.compareOp],
};
+ /* From the Broadwell PRM:
+ *
+ * "If Depth_Test_Enable = 1 AND Depth_Test_func = EQUAL, the
+ * Depth_Write_Enable must be set to 0."
+ */
+ if (info->depthTestEnable && info->depthCompareOp == VK_COMPARE_OP_EQUAL)
+ wm_depth_stencil.DepthBufferWriteEnable = false;
+
GENX(3DSTATE_WM_DEPTH_STENCIL_pack)(NULL, dw, &wm_depth_stencil);
}