diff options
author | Jason Ekstrand <[email protected]> | 2016-04-28 15:37:39 -0700 |
---|---|---|
committer | Jason Ekstrand <[email protected]> | 2016-05-14 13:34:25 -0700 |
commit | bee160b31be9e09eeab83f62d26ac331f08955fa (patch) | |
tree | e0446c57d900f30d17419758c3ea3b37c24ded4a /src/intel/vulkan/gen8_pipeline.c | |
parent | 7be100ac9af52b1ab5e2c34b45aba0d66304d55a (diff) |
i965/fs: Organize prog_data by ksp number rather than SIMD width
The hardware packets organize kernel pointers and GRF start by slots that
don't map directly to dispatch width. This means that all of the state
setup code has to re-arrange the data from prog_data into these slots.
This logic has been duplicated 4 times in the GL driver and one more time
in the Vulkan driver. Let's just put it all in brw_fs.cpp.
Reviewed-by: Kenneth Graunke <[email protected]>
Diffstat (limited to 'src/intel/vulkan/gen8_pipeline.c')
-rw-r--r-- | src/intel/vulkan/gen8_pipeline.c | 12 |
1 files changed, 7 insertions, 5 deletions
diff --git a/src/intel/vulkan/gen8_pipeline.c b/src/intel/vulkan/gen8_pipeline.c index 857f9798111..d96669494a2 100644 --- a/src/intel/vulkan/gen8_pipeline.c +++ b/src/intel/vulkan/gen8_pipeline.c @@ -502,9 +502,9 @@ genX(graphics_pipeline_create)( anv_batch_emit(&pipeline->batch, GENX(3DSTATE_PS), ps) { ps.KernelStartPointer0 = pipeline->ps_ksp0; ps.KernelStartPointer1 = 0; - ps.KernelStartPointer2 = pipeline->ps_ksp2; - ps._8PixelDispatchEnable = pipeline->ps_simd8 != NO_KERNEL; - ps._16PixelDispatchEnable = pipeline->ps_simd16 != NO_KERNEL; + ps.KernelStartPointer2 = pipeline->ps_ksp0 + wm_prog_data->prog_offset_2; + ps._8PixelDispatchEnable = wm_prog_data->dispatch_8; + ps._16PixelDispatchEnable = wm_prog_data->dispatch_16; ps._32PixelDispatchEnable = false; ps.SingleProgramFlow = false; ps.VectorMaskEnable = true; @@ -518,9 +518,11 @@ genX(graphics_pipeline_create)( ps.ScratchSpaceBasePointer = pipeline->scratch_start[MESA_SHADER_FRAGMENT]; ps.PerThreadScratchSpace = scratch_space(&wm_prog_data->base); - ps.DispatchGRFStartRegisterForConstantSetupData0 = pipeline->ps_grf_start0; + ps.DispatchGRFStartRegisterForConstantSetupData0 = + wm_prog_data->base.dispatch_grf_start_reg; ps.DispatchGRFStartRegisterForConstantSetupData1 = 0; - ps.DispatchGRFStartRegisterForConstantSetupData2 = pipeline->ps_grf_start2; + ps.DispatchGRFStartRegisterForConstantSetupData2 = + wm_prog_data->dispatch_grf_start_reg_2; } bool per_sample_ps = pCreateInfo->pMultisampleState && |