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authorJason Ekstrand <[email protected]>2016-03-04 10:45:24 -0800
committerJason Ekstrand <[email protected]>2016-03-04 12:03:00 -0800
commitec18fef88d8a7a1a3541b0d40708a6637412f50e (patch)
tree483283fddd7511a789de1dadb93ba5687c2e9758 /src/intel/vulkan/gen7_cmd_buffer.c
parentfcd8e571851c18a259fdc4ccb34f6ba23f3d29ea (diff)
anv/pipeline: Set StencilBufferWriteEnable from the pipeline
The hardware docs say that StencilBufferWriteEnable should only be set if StencilTestEnable is set. It seems reasonable to set them together.
Diffstat (limited to 'src/intel/vulkan/gen7_cmd_buffer.c')
-rw-r--r--src/intel/vulkan/gen7_cmd_buffer.c3
1 files changed, 0 insertions, 3 deletions
diff --git a/src/intel/vulkan/gen7_cmd_buffer.c b/src/intel/vulkan/gen7_cmd_buffer.c
index 1713cc17836..71010583129 100644
--- a/src/intel/vulkan/gen7_cmd_buffer.c
+++ b/src/intel/vulkan/gen7_cmd_buffer.c
@@ -581,9 +581,6 @@ genX(cmd_buffer_flush_state)(struct anv_cmd_buffer *cmd_buffer)
struct anv_dynamic_state *d = &cmd_buffer->state.dynamic;
struct GENX(DEPTH_STENCIL_STATE) depth_stencil = {
- .StencilBufferWriteEnable = d->stencil_write_mask.front != 0 ||
- d->stencil_write_mask.back != 0,
-
.StencilTestMask = d->stencil_compare_mask.front & 0xff,
.StencilWriteMask = d->stencil_write_mask.front & 0xff,