diff options
author | Jason Ekstrand <[email protected]> | 2016-08-25 01:49:49 -0700 |
---|---|---|
committer | Jason Ekstrand <[email protected]> | 2016-08-30 15:08:23 -0700 |
commit | 10f9901bcef7724cb72fb2fe7e3dd8d6660d2f34 (patch) | |
tree | 007712bd01daea07fe9389b2aad6de234d45df77 /src/intel/vulkan/anv_private.h | |
parent | 689971847005219178f5a484dffecf9e5e515192 (diff) |
anv: Rework pipeline caching
The original pipeline cache the Kristian wrote was based on a now-false
premise that the shaders can be stored in the pipeline cache. The Vulkan
1.0 spec explicitly states that the pipeline cache object is transiant and
you are allowed to delete it after using it to create a pipeline with no
ill effects. As nice as Kristian's design was, it doesn't jive with the
expectation provided by the Vulkan spec.
The new pipeline cache uses reference-counted anv_shader_bin objects that
are backed by a large state pool. The cache itself is just a hash table
mapping keys hashes to anv_shader_bin objects. This has the added
advantage of removing one more hand-rolled hash table from mesa.
Signed-off-by: Jason Ekstrand <[email protected]>
Cc: "12.0" <[email protected]>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=97476
Acked-by: Kristian Høgsberg Kristensen <[email protected]>
Diffstat (limited to 'src/intel/vulkan/anv_private.h')
-rw-r--r-- | src/intel/vulkan/anv_private.h | 72 |
1 files changed, 30 insertions, 42 deletions
diff --git a/src/intel/vulkan/anv_private.h b/src/intel/vulkan/anv_private.h index 878bbaa7678..f24020cb810 100644 --- a/src/intel/vulkan/anv_private.h +++ b/src/intel/vulkan/anv_private.h @@ -400,7 +400,7 @@ struct anv_fixed_size_state_pool { }; #define ANV_MIN_STATE_SIZE_LOG2 6 -#define ANV_MAX_STATE_SIZE_LOG2 10 +#define ANV_MAX_STATE_SIZE_LOG2 17 #define ANV_STATE_BUCKETS (ANV_MAX_STATE_SIZE_LOG2 - ANV_MIN_STATE_SIZE_LOG2 + 1) @@ -658,31 +658,27 @@ struct anv_queue { struct anv_pipeline_cache { struct anv_device * device; - struct anv_state_stream program_stream; pthread_mutex_t mutex; - uint32_t total_size; - uint32_t table_size; - uint32_t kernel_count; - uint32_t * hash_table; + struct hash_table * cache; }; struct anv_pipeline_bind_map; void anv_pipeline_cache_init(struct anv_pipeline_cache *cache, - struct anv_device *device); + struct anv_device *device, + bool cache_enabled); void anv_pipeline_cache_finish(struct anv_pipeline_cache *cache); -uint32_t anv_pipeline_cache_search(struct anv_pipeline_cache *cache, - const unsigned char *sha1, - const struct brw_stage_prog_data **prog_data, - struct anv_pipeline_bind_map *map); -uint32_t anv_pipeline_cache_upload_kernel(struct anv_pipeline_cache *cache, - const unsigned char *sha1, - const void *kernel, - size_t kernel_size, - const struct brw_stage_prog_data **prog_data, - size_t prog_data_size, - struct anv_pipeline_bind_map *map); + +struct anv_shader_bin * +anv_pipeline_cache_search(struct anv_pipeline_cache *cache, + const void *key, uint32_t key_size); +struct anv_shader_bin * +anv_pipeline_cache_upload_kernel(struct anv_pipeline_cache *cache, + const void *key_data, uint32_t key_size, + const void *kernel_data, uint32_t kernel_size, + const void *prog_data, uint32_t prog_data_size, + const struct anv_pipeline_bind_map *bind_map); struct anv_device { VK_LOADER_DATA _loader_data; @@ -705,7 +701,6 @@ struct anv_device { struct anv_block_pool instruction_block_pool; struct anv_state_pool instruction_state_pool; - struct anv_pipeline_cache default_pipeline_cache; struct anv_block_pool surface_state_block_pool; struct anv_state_pool surface_state_pool; @@ -1519,12 +1514,12 @@ struct anv_pipeline { struct anv_dynamic_state dynamic_state; struct anv_pipeline_layout * layout; - struct anv_pipeline_bind_map bindings[MESA_SHADER_STAGES]; bool use_repclear; bool needs_data_cache; - const struct brw_stage_prog_data * prog_data[MESA_SHADER_STAGES]; + struct anv_shader_bin * shaders[MESA_SHADER_STAGES]; + struct { uint32_t start[MESA_SHADER_GEOMETRY + 1]; uint32_t size[MESA_SHADER_GEOMETRY + 1]; @@ -1574,29 +1569,22 @@ anv_pipeline_has_stage(const struct anv_pipeline *pipeline, return (pipeline->active_stages & mesa_to_vk_shader_stage(stage)) != 0; } -static inline const struct brw_vs_prog_data * -get_vs_prog_data(struct anv_pipeline *pipeline) -{ - return (const struct brw_vs_prog_data *) pipeline->prog_data[MESA_SHADER_VERTEX]; +#define ANV_DECL_GET_PROG_DATA_FUNC(prefix, stage) \ +static inline const struct brw_##prefix##_prog_data * \ +get_##prefix##_prog_data(struct anv_pipeline *pipeline) \ +{ \ + if (anv_pipeline_has_stage(pipeline, stage)) { \ + return (const struct brw_##prefix##_prog_data *) \ + anv_shader_bin_get_prog_data(pipeline->shaders[stage]); \ + } else { \ + return NULL; \ + } \ } -static inline const struct brw_gs_prog_data * -get_gs_prog_data(struct anv_pipeline *pipeline) -{ - return (const struct brw_gs_prog_data *) pipeline->prog_data[MESA_SHADER_GEOMETRY]; -} - -static inline const struct brw_wm_prog_data * -get_wm_prog_data(struct anv_pipeline *pipeline) -{ - return (const struct brw_wm_prog_data *) pipeline->prog_data[MESA_SHADER_FRAGMENT]; -} - -static inline const struct brw_cs_prog_data * -get_cs_prog_data(struct anv_pipeline *pipeline) -{ - return (const struct brw_cs_prog_data *) pipeline->prog_data[MESA_SHADER_COMPUTE]; -} +ANV_DECL_GET_PROG_DATA_FUNC(vs, MESA_SHADER_VERTEX) +ANV_DECL_GET_PROG_DATA_FUNC(gs, MESA_SHADER_GEOMETRY) +ANV_DECL_GET_PROG_DATA_FUNC(wm, MESA_SHADER_FRAGMENT) +ANV_DECL_GET_PROG_DATA_FUNC(cs, MESA_SHADER_COMPUTE) struct anv_graphics_pipeline_create_info { /** |