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authorCaio Marcelo de Oliveira Filho <[email protected]>2018-09-21 16:07:38 -0700
committerMarge Bot <[email protected]>2020-04-07 17:16:09 +0000
commit395de69b1febf4cfca29482e1ff7ddd2ae400d8b (patch)
treea9a63e938be900cf535fdc734c0281edc2ef348e /src/intel/vulkan/anv_pipeline.c
parentafa5447312352cd68d4688d9521cb1de25a9939c (diff)
intel/fs: Allow multiple slots for position
Change brw_compute_vue_map() to also take the number of pos slots. If more than one slot is used, the VARYING_SLOT_POS is treated as an array. When using Primitive Replication, instead of a single position, the VUE must contain an array of positions. Padding might be necessary (after clip distance) to ensure rest of attributes start aligned. v2: Add note about array in the commit message and assert that pos_slots >= 1 to make clear 0 is invalid. (Jason) Move padding to be after the clip distance. v3: Apply the correct offset when gathering the sources from outputs. Reviewed-by: Jason Ekstrand <[email protected]> [v2] Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Rafael Antognolli <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/2313>
Diffstat (limited to 'src/intel/vulkan/anv_pipeline.c')
-rw-r--r--src/intel/vulkan/anv_pipeline.c4
1 files changed, 2 insertions, 2 deletions
diff --git a/src/intel/vulkan/anv_pipeline.c b/src/intel/vulkan/anv_pipeline.c
index 12dcb024acb..c1d0e393a96 100644
--- a/src/intel/vulkan/anv_pipeline.c
+++ b/src/intel/vulkan/anv_pipeline.c
@@ -741,7 +741,7 @@ anv_pipeline_compile_vs(const struct brw_compiler *compiler,
brw_compute_vue_map(compiler->devinfo,
&vs_stage->prog_data.vs.base.vue_map,
vs_stage->nir->info.outputs_written,
- vs_stage->nir->info.separate_shader);
+ vs_stage->nir->info.separate_shader, 1);
vs_stage->num_stats = 1;
vs_stage->code = brw_compile_vs(compiler, device, mem_ctx,
@@ -887,7 +887,7 @@ anv_pipeline_compile_gs(const struct brw_compiler *compiler,
brw_compute_vue_map(compiler->devinfo,
&gs_stage->prog_data.gs.base.vue_map,
gs_stage->nir->info.outputs_written,
- gs_stage->nir->info.separate_shader);
+ gs_stage->nir->info.separate_shader, 1);
gs_stage->num_stats = 1;
gs_stage->code = brw_compile_gs(compiler, device, mem_ctx,