diff options
author | Jason Ekstrand <[email protected]> | 2018-01-18 09:17:17 -0800 |
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committer | Jason Ekstrand <[email protected]> | 2018-02-08 16:35:31 -0800 |
commit | 2e69045c4d37f5ddd56b284b225a7f11a374381c (patch) | |
tree | 5d5a907be4b11c2428e8545310f15452a9f077a7 /src/intel/vulkan/anv_image.c | |
parent | f0523f70ef4e3788a4510581c641dcea51640417 (diff) |
anv/image: Simplify some verbose commennts
Reviewed-by: Topi Pohjolainen <[email protected]>
Reviewed-by: Nanley Chery <[email protected]>
Diffstat (limited to 'src/intel/vulkan/anv_image.c')
-rw-r--r-- | src/intel/vulkan/anv_image.c | 13 |
1 files changed, 3 insertions, 10 deletions
diff --git a/src/intel/vulkan/anv_image.c b/src/intel/vulkan/anv_image.c index 583e085cf94..11942d0f320 100644 --- a/src/intel/vulkan/anv_image.c +++ b/src/intel/vulkan/anv_image.c @@ -235,18 +235,11 @@ add_fast_clear_state_buffer(struct anv_image *image, assert(image->planes[plane].aux_surface.isl.size > 0 && image->aspects & VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV); - /* The offset to the buffer of clear values must be dword-aligned for GPU - * memcpy operations. It is located immediately after the auxiliary surface. - */ - - /* Tiled images are guaranteed to be 4K aligned, so the image alignment - * should also be dword-aligned. + /* Compressed images must be tiled and therefore everything should be 4K + * aligned. The CCS has the same alignment requirements. This is good + * because we need at least dword-alignment for MI_LOAD/STORE operations. */ assert(image->alignment % 4 == 0); - - /* Auxiliary buffers should be a multiple of 4K, so the start of the clear - * values buffer should already be dword-aligned. - */ assert((image->planes[plane].offset + image->planes[plane].size) % 4 == 0); /* This buffer should be at the very end of the plane. */ |