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author | Lionel Landwerlin <[email protected]> | 2017-05-30 20:06:48 +0100 |
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committer | Lionel Landwerlin <[email protected]> | 2017-06-06 14:04:37 +0100 |
commit | 2ef73473c8eedab679637334a0af597d26222e0a (patch) | |
tree | 43c31ddabf9bfcf589fdc13e203b98460f728661 /src/intel/vulkan/anv_dump.c | |
parent | 6c655cfeb49a8142c44782c5164619a5860c7706 (diff) |
intel: gen-decoder: rework how we handle groups
The current way of handling groups doesn't seem to be able to handle
MI_LOAD_REGISTER_* with more than one register. This change reworks
the way we handle groups by building a traversal list on loading the
GENXML files.
Let's say you have
Instruction {
Field0
Field1
Field2
Group0 (count=2) {
Field0-0
Field0-1
}
Group1 (count=4) {
Field1-0
Field1-1
}
}
We build of linked on load that goes :
Instruction -> Group0 -> Group1
All of those are gen_group structures, making the traversal trivial.
We just need to iterate groups for the right number of timers (count
field in genxml).
The more fancy case is when you have only a single group of unknown
size (count=0). In that case we keep on reading that group for as long
as we're within the DWordLength of that instruction.
Signed-off-by: Lionel Landwerlin <[email protected]>
Reviewed-by: Rafael Antognolli <[email protected]>
Diffstat (limited to 'src/intel/vulkan/anv_dump.c')
0 files changed, 0 insertions, 0 deletions