summaryrefslogtreecommitdiffstats
path: root/src/intel/tools/tests/gen9/csel.expected
diff options
context:
space:
mode:
authorSagar Ghuge <[email protected]>2019-03-22 19:13:54 -0700
committerMatt Turner <[email protected]>2019-05-07 14:33:48 -0700
commit4e828bb48abf12d43c2b4a373b4b2125c90ea152 (patch)
tree71d021ec2939a0d9dcdb78a35ff3419ecfb8f78c /src/intel/tools/tests/gen9/csel.expected
parent1fb5ce0a11ccb8a0f8d41d0499f8a16b1dfef379 (diff)
intel/tools: Add unit tests for assembler
v1: Pass executable object from meson to test(Dylan Baker) v2: Ignore generated output files from git status(Matt Turner) Signed-off-by: Sagar Ghuge <[email protected]> Reviewed-by: Matt Turner <[email protected]> Reviewed-by: Dylan Baker <[email protected]>
Diffstat (limited to 'src/intel/tools/tests/gen9/csel.expected')
-rw-r--r--src/intel/tools/tests/gen9/csel.expected13
1 files changed, 13 insertions, 0 deletions
diff --git a/src/intel/tools/tests/gen9/csel.expected b/src/intel/tools/tests/gen9/csel.expected
new file mode 100644
index 00000000000..300b9154107
--- /dev/null
+++ b/src/intel/tools/tests/gen9/csel.expected
@@ -0,0 +1,13 @@
+12 01 60 02 80 00 1e 0f c8 b1 00 39 16 20 c7 02
+12 01 80 02 80 00 1e 0e c8 81 00 39 10 20 07 02
+12 01 60 06 20 00 1e 15 01 56 20 00 0a 04 58 01
+12 01 60 05 40 00 1e 6b c8 51 06 39 ca 20 07 1a
+12 01 60 06 80 00 1e 15 01 50 20 40 0a 04 48 01
+12 01 60 05 00 00 1e 7f c8 21 00 39 10 04 00 01
+12 01 80 05 00 00 1e 7e c8 21 00 39 1a 04 80 01
+12 01 80 06 20 00 1e 0d c8 91 04 39 74 20 47 12
+12 01 80 06 80 00 1e 0f c8 a1 03 39 92 20 47 12
+12 01 80 05 40 00 1e 45 c8 11 04 39 82 20 c7 10
+12 01 60 83 00 00 1e 7d 01 26 20 80 04 04 80 00
+12 01 60 03 00 00 1e 7d 01 26 20 80 04 04 80 00
+12 01 80 03 00 00 1e 7a 01 26 20 80 04 04 80 00