diff options
author | Sagar Ghuge <[email protected]> | 2019-03-22 19:13:54 -0700 |
---|---|---|
committer | Matt Turner <[email protected]> | 2019-05-07 14:33:48 -0700 |
commit | 4e828bb48abf12d43c2b4a373b4b2125c90ea152 (patch) | |
tree | 71d021ec2939a0d9dcdb78a35ff3419ecfb8f78c /src/intel/tools/tests/gen8/and.asm | |
parent | 1fb5ce0a11ccb8a0f8d41d0499f8a16b1dfef379 (diff) |
intel/tools: Add unit tests for assembler
v1: Pass executable object from meson to test(Dylan Baker)
v2: Ignore generated output files from git status(Matt Turner)
Signed-off-by: Sagar Ghuge <[email protected]>
Reviewed-by: Matt Turner <[email protected]>
Reviewed-by: Dylan Baker <[email protected]>
Diffstat (limited to 'src/intel/tools/tests/gen8/and.asm')
-rw-r--r-- | src/intel/tools/tests/gen8/and.asm | 29 |
1 files changed, 29 insertions, 0 deletions
diff --git a/src/intel/tools/tests/gen8/and.asm b/src/intel/tools/tests/gen8/and.asm new file mode 100644 index 00000000000..49dc122806c --- /dev/null +++ b/src/intel/tools/tests/gen8/and.asm @@ -0,0 +1,29 @@ +and(8) g3<1>UD g2<0,1,0>UD ~g2.2<0,1,0>D { align1 1Q }; +and(16) g3<1>UD g2<0,1,0>UD ~g2.2<0,1,0>D { align1 1H }; +and(8) g8<1>UD g0.1<0,1,0>UW 0x07ffUW { align1 1Q }; +and(16) g20<1>UD g0.1<0,1,0>UW 0x07ffUW { align1 1H }; +and.z.f0.0(8) g9<1>UD g8<8,8,1>UD 0x00000003UD { align1 1Q }; +and(16) g120<1>D g7<8,8,1>D g2<8,8,1>D { align1 1H }; +and.z.f0.0(8) null<1>UD g13<8,8,1>UD g12<8,8,1>UD { align1 1Q }; +and.nz.f0.0(8) null<1>UD g4.1<0,1,0>UD g19<8,8,1>UD { align1 1Q }; +and.z.f0.0(16) null<1>UD g27<8,8,1>UD g18<8,8,1>UD { align1 1H }; +and.nz.f0.0(16) null<1>UD g6.1<0,1,0>UD g22<8,8,1>UD { align1 1H }; +and(1) g7<1>UD g5<0,1,0>UD 0x000000f0UD { align1 WE_all 1N }; +and.z.f0.0(16) g21<1>UD g19<8,8,1>UD g17<8,8,1>UD { align1 1H }; +and(8) g61<1>UD g79<8,8,1>UD g32.1<8,4,2>UD { align1 2Q }; +and(8) g96<1>D ~g94<8,8,1>D ~g95<8,8,1>D { align1 1Q }; +and(1) a0<1>UD g4<0,1,0>UD 0x000000ffUD { align1 WE_all 1N }; +and(16) g66<1>UD g40<8,8,1>UD 0x0000003fUD { align1 2H }; +and(1) g2<1>UD g20<0,1,0>UD 0x000000ffUD { align1 WE_all 3N }; +and.z.f0.0(8) null<1>D g13<8,8,1>UD 0x0000001fUD { align1 1Q }; +and(8) g21<1>UD g15<8,8,1>UD 0x00000003UD { align1 WE_all 1Q }; +and(8) g4<1>UW g3<8,8,1>UW 0xfffcUW { align1 1Q }; +and(16) g13<1>UW g19<16,8,2>UW 0xfffcUW { align1 1H }; +and.nz.f0.0(8) null<1>UD ~g2.2<0,1,0>D g9<8,8,1>UD { align1 1Q }; +and(8) g18<1>UD ~g2.2<0,1,0>D g7<8,8,1>UD { align1 1Q }; +and.nz.f0.0(16) null<1>UD ~g2.2<0,1,0>D g14<8,8,1>UD { align1 1H }; +and(16) g30<1>UD ~g2.2<0,1,0>D g10<8,8,1>UD { align1 1H }; +and.nz.f0.0(8) g10<1>UD g9<8,8,1>UD 0x00000001UD { align1 1Q }; +and.nz.f0.0(16) g16<1>UD g14<8,8,1>UD 0x00000001UD { align1 1H }; +and(8) g12<1>UQ g9<4,4,1>UQ g11<4,4,1>UQ { align1 1Q }; +and(8) g26<1>UQ g18<4,4,1>UQ g22<4,4,1>UQ { align1 2Q }; |