diff options
| author | Sagar Ghuge <[email protected]> | 2019-03-22 19:13:54 -0700 |
|---|---|---|
| committer | Matt Turner <[email protected]> | 2019-05-07 14:33:48 -0700 |
| commit | 4e828bb48abf12d43c2b4a373b4b2125c90ea152 (patch) | |
| tree | 71d021ec2939a0d9dcdb78a35ff3419ecfb8f78c /src/intel/tools/tests/gen4/mul.asm | |
| parent | 1fb5ce0a11ccb8a0f8d41d0499f8a16b1dfef379 (diff) | |
intel/tools: Add unit tests for assembler
v1: Pass executable object from meson to test(Dylan Baker)
v2: Ignore generated output files from git status(Matt Turner)
Signed-off-by: Sagar Ghuge <[email protected]>
Reviewed-by: Matt Turner <[email protected]>
Reviewed-by: Dylan Baker <[email protected]>
Diffstat (limited to 'src/intel/tools/tests/gen4/mul.asm')
| -rw-r--r-- | src/intel/tools/tests/gen4/mul.asm | 37 |
1 files changed, 37 insertions, 0 deletions
diff --git a/src/intel/tools/tests/gen4/mul.asm b/src/intel/tools/tests/gen4/mul.asm new file mode 100644 index 00000000000..82629fae802 --- /dev/null +++ b/src/intel/tools/tests/gen4/mul.asm @@ -0,0 +1,37 @@ +mul(16) g16<1>F g14<8,8,1>F g12<8,8,1>F { align1 compr }; +mul(8) g8<1>.xyzF g6<4>.xyzzF g8<4>.wF { align16 }; +mul(8) g9<1>.wUD g7<4>.wF 0x45000000F /* 2048F */ { align16 }; +mul(8) g8<1>.xD g8<4>.xD g5<0>.xD { align16 }; +mul(8) g8<1>.xD g8<4>.xD 32D { align16 }; +mul(16) m2<1>F g4<8,8,1>F g8.3<0,1,0>F { align1 compr }; +mul(16) g22<1>F g16<8,8,1>F 0x41800000F /* 16F */ { align1 compr }; +mul(8) m5<1>.xyF g3<4>.xyyyF 0x3f000000F /* 0.5F */ { align16 NoDDClr }; +mul(8) g5<1>F g3<4>F 0x37800000F /* 1.52588e-05F */ { align16 }; +mul.sat(16) m2<1>F g16<8,8,1>F g6<8,8,1>F { align1 compr }; +mul(8) acc0<1>D g1<0>.xD g1<0>.yD { align16 }; +mul(8) m5<1>F g3<4>F 0x3f000000F /* 0.5F */ { align16 }; +mul(16) g4<1>D g6<8,8,1>D g2<0,1,0>D { align1 compr }; +mul.sat(16) g18<1>F g16<8,8,1>F g14<8,8,1>F { align1 compr }; +mul(8) g4<1>F g4<8,8,1>F g55<8,8,1>F { align1 }; +mul(8) g26<1>.wUD g29<4>.wF 0x45000000F /* 2048F */ { align16 NoDDChk }; +mul(8) g2<1>.xyzF g2<4>.wF 0x40404830VF /* [1F, 3F, 2F, 2F]VF */ { align16 }; +mul(16) g4<1>D g2<0,1,0>UW g2.2<0,1,0>D { align1 compr }; +mul(16) m8<1>F g24<8,8,1>F 0x3f000000F /* 0.5F */ { align1 compr }; +mul.sat(8) g6<1>.xyzF g6<4>.xyzzF g7<4>.xF { align16 }; +mul.sat(8) m5<1>F g6<4>F 0x3b800000F /* 0.00390625F */ { align16 }; +mul.sat(8) m5<1>.xyzF g3<4>.xyzzF 0x3f000000F /* 0.5F */ { align16 NoDDClr }; +mul.g.f0.0(16) null<1>F g18<8,8,1>F g12<8,8,1>F { align1 compr }; +mul.sat(8) m5<1>F g3<4>F g3<4>F { align16 }; +mul.l.f0.0(8) null<1>.xF g1<0>.zF g1<0>.yF { align16 }; +mul.l.f0.0(16) null<1>F g2.2<0,1,0>F g2.1<0,1,0>F { align1 compr }; +mul.l.f0.0(16) g16<1>F g14<8,8,1>F g12<8,8,1>F { align1 compr }; +mul.nz.f0.0(16) g18<1>F g16<8,8,1>F g12<8,8,1>F { align1 compr }; +mul.sat(8) m6<1>.xyzF g32<4>.xF g30<4>.xyzzF { align16 NoDDClr }; +mul.nz.f0.0(16) g6<1>F g4<8,8,1>F 0x3f808000F /* 1.00391F */ { align1 compr }; +mul.sat(8) m5<1>F g4<4>F 0x20303030VF /* [1F, 1F, 1F, 0.5F]VF */ { align16 }; +mul(8) m5<1>F g3<4>F 0x20305454VF /* [5F, 5F, 1F, 0.5F]VF */ { align16 }; +mul(8) m6<1>.xyzF g12<4>.xyzzF g13<4>.xF { align16 NoDDClr }; +mul(8) m5<1>.xyzF g3<4>.xyzzF 0x30302020VF /* [0.5F, 0.5F, 1F, 1F]VF */ { align16 NoDDClr }; +mul(8) m5<1>.zF g3<4>.zF 0x3f000000F /* 0.5F */ { align16 NoDDClr,NoDDChk }; +mul(8) m5<1>F g3<4>F g1<0>.xF { align16 }; +mul.sat(8) m5<1>.xyzF g7<4>.xF 0x3030VF /* [1F, 1F, 0F, 0F]VF */ { align16 NoDDClr }; |