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| author | Sagar Ghuge <[email protected]> | 2019-05-29 11:43:30 -0700 |
|---|---|---|
| committer | Sagar Ghuge <[email protected]> | 2019-07-01 10:14:22 -0700 |
| commit | 83fdec0f0deb98a7f48186679a491f3128fdd1fe (patch) | |
| tree | cfda74c5ed1cc80dc029c0706cb17d705c54932a /src/intel/tools/tests/gen4.5/cont.expected | |
| parent | 8d74749f812e64968d37266061293e204fea252c (diff) | |
intel/compiler: Enable the emission of ROR/ROL instructions
v2: 1) Drop changes for vec4 backend as on Gen11+ we don't support
align16 mode (Matt Turner)
Signed-off-by: Sagar Ghuge <[email protected]>
Reviewed-by: Matt Turner <[email protected]>
Diffstat (limited to 'src/intel/tools/tests/gen4.5/cont.expected')
0 files changed, 0 insertions, 0 deletions