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| author | Iago Toral Quiroga <[email protected]> | 2018-05-21 14:42:42 +0200 |
|---|---|---|
| committer | Juan A. Suarez Romero <[email protected]> | 2019-04-18 11:05:18 +0200 |
| commit | 120c970619cd876a256f788afe2a79a92f8cd7ab (patch) | |
| tree | 313d5ad6a5f9db5294e86ac83dc0c35d36d8f9f7 /src/intel/meson.build | |
| parent | 4ab2b97a8fbc8fb07534ec92c9c5326889af290f (diff) | |
intel/compiler: add new half-float register type for 3-src instructions
This is available since gen8.
v2: restore previously existing assertion.
v3: don't use separate tables for gen7 and gen8, just assert that we
don't use half-float before gen8 (Matt)
Reviewed-by: Topi Pohjolainen <[email protected]> (v1)
Reviewed-by: Jason Ekstrand <[email protected]>
Diffstat (limited to 'src/intel/meson.build')
0 files changed, 0 insertions, 0 deletions