diff options
author | Samuel Iglesias Gonsálvez <[email protected]> | 2019-02-15 09:07:29 +0100 |
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committer | Samuel Iglesias Gonsálvez <[email protected]> | 2019-02-20 08:28:31 +0100 |
commit | 63a919a3ceed705b01c4bf31dbbef28997b04d6c (patch) | |
tree | e01004baae09cda795dbabcd8dd2826edf228f20 /src/intel/isl | |
parent | 572854e706043353d28aa41e6dc7bbdc35de8029 (diff) |
isl: remove the cache line size alignment requirement
The cacheline size was a requirement for using the BLT engine, which
we don't use anymore except for a few things on old HW, so we drop it.
Fixes CTS's CL#3500 test:
dEQP-VK.api.image_clearing.core.clear_color_image.2d.linear.single_layer.r8g8b8_unorm
Signed-off-by: Samuel Iglesias Gonsálvez <[email protected]>
Reviewed-by: Jason Ekstrand <[email protected]>
Diffstat (limited to 'src/intel/isl')
-rw-r--r-- | src/intel/isl/isl.c | 14 |
1 files changed, 0 insertions, 14 deletions
diff --git a/src/intel/isl/isl.c b/src/intel/isl/isl.c index eaaa28014a3..5c34efb9a13 100644 --- a/src/intel/isl/isl.c +++ b/src/intel/isl/isl.c @@ -1381,20 +1381,6 @@ isl_calc_row_pitch(const struct isl_device *dev, uint32_t alignment_B = isl_calc_row_pitch_alignment(surf_info, tile_info); - /* If pitch isn't given and it can be chosen freely, align it by cache line - * allowing one to use blit engine on the surface. - */ - if (surf_info->row_pitch_B == 0 && tile_info->tiling == ISL_TILING_LINEAR) { - /* From the Broadwell PRM docs for XY_SRC_COPY_BLT::SourceBaseAddress: - * - * "Base address of the destination surface: X=0, Y=0. Lower 32bits - * of the 48bit addressing. When Src Tiling is enabled (Bit_15 - * enabled), this address must be 4KB-aligned. When Tiling is not - * enabled, this address should be CL (64byte) aligned." - */ - alignment_B = MAX2(alignment_B, 64); - } - const uint32_t min_row_pitch_B = isl_calc_min_row_pitch(dev, surf_info, tile_info, phys_total_el, alignment_B); |