diff options
| author | Rob Clark <[email protected]> | 2019-02-27 09:56:18 -0500 |
|---|---|---|
| committer | Rob Clark <[email protected]> | 2019-03-03 13:27:50 -0500 |
| commit | 00f838fa730f5c765902fe2e5ce9754df5276e91 (patch) | |
| tree | 9b855a29283e348829a004644baf3222d257e91c /src/intel/isl | |
| parent | 8a5f2d9444879dc4c8b2b1f192b2a667a1278a2b (diff) | |
freedreno/ir3: track register pressure in sched
Not a perfect solution, and the "pressure" target is hard-coded. But it
doesn't really seem to much in the common case, and avoids exploding
register usage in dEQP ssbo tests.
So this should serve as a stop-gap solution until I have time to re-
write the scheduler.
Hurts slightly in instruction count, but gains (reduces) slightly the
register usage in shader-db. Fixes ~150 dEQP-GLES31.functional.ssbo.*
that were failing due to RA fail.
Signed-off-by: Rob Clark <[email protected]>
Diffstat (limited to 'src/intel/isl')
0 files changed, 0 insertions, 0 deletions