diff options
| author | Jason Ekstrand <[email protected]> | 2016-07-08 19:37:27 -0700 |
|---|---|---|
| committer | Jason Ekstrand <[email protected]> | 2016-07-13 11:47:37 -0700 |
| commit | 219024b9a7588a5ebe7faf46120e8e5842e24b43 (patch) | |
| tree | 1040549e41cc74a55b90dab1198590873130892b /src/intel/isl | |
| parent | 33dc8549fb9b227a57a84aac53f17bd099da38f4 (diff) | |
isl: Add support for multisample compression surfaces
Reviewed-by: Chad Versace <[email protected]>
Diffstat (limited to 'src/intel/isl')
| -rw-r--r-- | src/intel/isl/isl.h | 7 | ||||
| -rw-r--r-- | src/intel/isl/isl_format_layout.csv | 4 | ||||
| -rw-r--r-- | src/intel/isl/isl_gen7.c | 4 |
3 files changed, 15 insertions, 0 deletions
diff --git a/src/intel/isl/isl.h b/src/intel/isl/isl.h index 8c01d6edb89..13882eb2e78 100644 --- a/src/intel/isl/isl.h +++ b/src/intel/isl/isl.h @@ -352,6 +352,10 @@ enum isl_format { /* Formats for color compression surfaces */ ISL_FORMAT_HIZ, + ISL_FORMAT_MCS_2X, + ISL_FORMAT_MCS_4X, + ISL_FORMAT_MCS_8X, + ISL_FORMAT_MCS_16X, /* Hardware doesn't understand this out-of-band value */ ISL_FORMAT_UNSUPPORTED = UINT16_MAX, @@ -403,6 +407,7 @@ enum isl_txc { /* Used for auxiliary surface formats */ ISL_TXC_HIZ, + ISL_TXC_MCS, }; /** @@ -519,6 +524,7 @@ typedef uint64_t isl_surf_usage_flags_t; #define ISL_SURF_USAGE_DISPLAY_FLIP_Y_BIT (1u << 11) #define ISL_SURF_USAGE_STORAGE_BIT (1u << 12) #define ISL_SURF_USAGE_HIZ_BIT (1u << 13) +#define ISL_SURF_USAGE_MCS_BIT (1u << 14) /** @} */ /** @@ -984,6 +990,7 @@ isl_format_has_bc_compression(enum isl_format fmt) return false; case ISL_TXC_HIZ: + case ISL_TXC_MCS: unreachable("Should not be called on an aux surface"); } diff --git a/src/intel/isl/isl_format_layout.csv b/src/intel/isl/isl_format_layout.csv index 3e681e8a4a4..972d50f1009 100644 --- a/src/intel/isl/isl_format_layout.csv +++ b/src/intel/isl/isl_format_layout.csv @@ -315,3 +315,7 @@ ASTC_LDR_2D_10X10_FLT16 , 128, 10, 10, 1, sf16, sf16, sf16, sf16, , ASTC_LDR_2D_12X10_FLT16 , 128, 12, 10, 1, sf16, sf16, sf16, sf16, , , , linear, astc ASTC_LDR_2D_12X12_FLT16 , 128, 12, 12, 1, sf16, sf16, sf16, sf16, , , , linear, astc HIZ , 128, 8, 4, 1, , , , , , , , , hiz +MCS_2X , 8, 1, 1, 1, , , , , , , , , mcs +MCS_4X , 8, 1, 1, 1, , , , , , , , , mcs +MCS_8X , 32, 1, 1, 1, , , , , , , , , mcs +MCS_16X , 64, 1, 1, 1, , , , , , , , , mcs diff --git a/src/intel/isl/isl_gen7.c b/src/intel/isl/isl_gen7.c index 1cdb52d3c4e..bb0ab38bc19 100644 --- a/src/intel/isl/isl_gen7.c +++ b/src/intel/isl/isl_gen7.c @@ -238,6 +238,10 @@ gen7_filter_tiling(const struct isl_device *dev, *flags &= ~ISL_TILING_HIZ_BIT; } + /* MCS buffers are always Y-tiled */ + if (isl_format_get_layout(info->format)->txc == ISL_TXC_MCS) + *flags &= ISL_TILING_Y0_BIT; + if (info->usage & (ISL_SURF_USAGE_DISPLAY_ROTATE_90_BIT | ISL_SURF_USAGE_DISPLAY_ROTATE_180_BIT | ISL_SURF_USAGE_DISPLAY_ROTATE_270_BIT)) { |