diff options
| author | Jason Ekstrand <[email protected]> | 2016-07-08 22:12:10 -0700 |
|---|---|---|
| committer | Jason Ekstrand <[email protected]> | 2016-07-13 11:47:37 -0700 |
| commit | 3ab3d97ac9d5851ce452b74822fff0c6c6694ad2 (patch) | |
| tree | f7bbc93966451b8d5f20fc0e73e00d826e4a6540 /src/intel/isl/isl_gen9.c | |
| parent | 219024b9a7588a5ebe7faf46120e8e5842e24b43 (diff) | |
isl: Add support for color control surfaces
Reviewed-by: Chad Versace <[email protected]>
Diffstat (limited to 'src/intel/isl/isl_gen9.c')
| -rw-r--r-- | src/intel/isl/isl_gen9.c | 12 |
1 files changed, 12 insertions, 0 deletions
diff --git a/src/intel/isl/isl_gen9.c b/src/intel/isl/isl_gen9.c index ff0dec955a5..9c76ccfc669 100644 --- a/src/intel/isl/isl_gen9.c +++ b/src/intel/isl/isl_gen9.c @@ -106,6 +106,18 @@ gen9_choose_image_alignment_el(const struct isl_device *dev, /* Handled by isl_choose_image_alignment_el */ assert(info->format != ISL_FORMAT_HIZ); + const struct isl_format_layout *fmtl = isl_format_get_layout(info->format); + if (fmtl->txc == ISL_TXC_CCS) { + /* Sky Lake PRM Vol. 7, "MCS Buffer for Render Target(s)" (p. 632): + * + * "Mip-mapped and arrayed surfaces are supported with MCS buffer + * layout with these alignments in the RT space: Horizontal + * Alignment = 128 and Vertical Alignment = 64." + */ + *image_align_el = isl_extent3d(128 / fmtl->bw, 64 / fmtl->bh, 1); + return; + } + /* This BSpec text provides some insight into the hardware's alignment * requirements [Skylake BSpec > Memory Views > Common Surface Formats > * Surface Layout and Tiling > 2D Surfaces]: |