diff options
author | Jason Ekstrand <[email protected]> | 2016-07-08 22:12:10 -0700 |
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committer | Jason Ekstrand <[email protected]> | 2016-07-13 11:47:37 -0700 |
commit | 3ab3d97ac9d5851ce452b74822fff0c6c6694ad2 (patch) | |
tree | f7bbc93966451b8d5f20fc0e73e00d826e4a6540 /src/intel/isl/isl_gen8.c | |
parent | 219024b9a7588a5ebe7faf46120e8e5842e24b43 (diff) |
isl: Add support for color control surfaces
Reviewed-by: Chad Versace <[email protected]>
Diffstat (limited to 'src/intel/isl/isl_gen8.c')
-rw-r--r-- | src/intel/isl/isl_gen8.c | 13 |
1 files changed, 13 insertions, 0 deletions
diff --git a/src/intel/isl/isl_gen8.c b/src/intel/isl/isl_gen8.c index ff35d5f868f..38a759ff08c 100644 --- a/src/intel/isl/isl_gen8.c +++ b/src/intel/isl/isl_gen8.c @@ -204,6 +204,19 @@ gen8_choose_image_alignment_el(const struct isl_device *dev, assert(!isl_tiling_is_std_y(tiling)); + const struct isl_format_layout *fmtl = isl_format_get_layout(info->format); + if (fmtl->txc == ISL_TXC_CCS) { + /* + * Broadwell PRM Vol 7, "MCS Buffer for Render Target(s)" (p. 676): + * + * "Mip-mapped and arrayed surfaces are supported with MCS buffer + * layout with these alignments in the RT space: Horizontal + * Alignment = 256 and Vertical Alignment = 128. + */ + *image_align_el = isl_extent3d(256 / fmtl->bw, 128 / fmtl->bh, 1); + return; + } + /* The below text from the Broadwell PRM provides some insight into the * hardware's requirements for LOD alignment. From the Broadwell PRM >> * Volume 5: Memory Views >> Surface Layout >> 2D Surfaces: |