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authorJason Ekstrand <[email protected]>2017-07-31 08:33:22 -0700
committerJason Ekstrand <[email protected]>2017-08-07 09:31:11 -0700
commitc15b92ce1160d742ea431062bbe4b3e818bb2aaf (patch)
tree6aaac7e554d03bf79fa0423d37dc0a924dba7e8e /src/intel/isl/isl_gen8.c
parent06d3115bb97740a4c8f36c645944a8bd0bde3f68 (diff)
intel/isl: Stop padding surfaces
The docs contain a bunch of commentary about the need to pad various surfaces out to multiples of something or other. However, all of those requirements are about avoiding GTT errors due to missing pages when the data port or sampler accesses slightly out-of-bounds. However, because the kernel already fills all the empty space in our GTT with the scratch page, we never have to worry about faulting due to OOB reads. There are two caveats to this: 1) There is some potential for issues with caches here if extra data ends up in a cache we don't expect due to OOB reads. However, because we always trash the entire cache whenever we need to move anything between cache domains, this shouldn't be an issue. 2) There is a potential issue if a surface gets placed at the very top of the GTT by the kernel. In this case, the hardware could potentially end up trying to read past the top of the GTT. If it nicely wraps around at the 48-bit (or 32-bit) boundary, then this shouldn't be an issue thanks to the scratch page. If it doesn't, then we need to come up with something to handle it. Up until some of the GL move to ISL, having the padding code in there just caused us to harmlessly use a bit more memory in Vulkan. However, now that we're using ISL sizes to validate external dma-buf images, these padding requirements are causing us to reject otherwise valid images due to the size of the BO being too small. Acked-by: Kenneth Graunke <[email protected]> Tested-by: Tapani Pälli <[email protected]> Tested-by: Tomasz Figa <[email protected]> Reviewed-by: Jordan Justen <[email protected]> Cc: "17.2" <[email protected]>
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