diff options
| author | Kenneth Graunke <[email protected]> | 2016-08-26 13:01:13 -0700 |
|---|---|---|
| committer | Kenneth Graunke <[email protected]> | 2016-09-15 21:21:50 -0700 |
| commit | 081f21f29bd6bee866ddb21d423ffa0506dd7bac (patch) | |
| tree | 2e2436f43c22e479653bb93159406497443c79e8 /src/intel/isl/isl_gen7.c | |
| parent | 9fec15a7e047eda52beb0cc71d7605656d91f685 (diff) | |
isl: Finish tiling filtering for Gen6.
Gen6 only has one additional restriction over Gen7+, so we just add it
to the existing gen7 function (which actually covers later gens too).
This should stop FINISHME spew when running GL on Sandybridge.
v2: Fix bytes per block vs. bits per block confusion (Jason) and
rename function to gen6_filter_tiling (Jason and Chad).
Signed-off-by: Kenneth Graunke <[email protected]>
Reviewed-by: Jason Ekstrand <[email protected]>
Diffstat (limited to 'src/intel/isl/isl_gen7.c')
| -rw-r--r-- | src/intel/isl/isl_gen7.c | 12 |
1 files changed, 11 insertions, 1 deletions
diff --git a/src/intel/isl/isl_gen7.c b/src/intel/isl/isl_gen7.c index f3d8428d059..4f1cc9d5f1a 100644 --- a/src/intel/isl/isl_gen7.c +++ b/src/intel/isl/isl_gen7.c @@ -198,7 +198,7 @@ gen7_format_needs_valign2(const struct isl_device *dev, * flags except ISL_TILING_X_BIT and ISL_TILING_LINEAR_BIT. */ void -gen7_filter_tiling(const struct isl_device *dev, +gen6_filter_tiling(const struct isl_device *dev, const struct isl_surf_init_info *restrict info, isl_tiling_flags_t *flags) { @@ -297,6 +297,16 @@ gen7_filter_tiling(const struct isl_device *dev, */ *flags &= ~ISL_TILING_Y0_BIT; } + + /* From the Sandybridge PRM, Volume 1, Part 2, page 32: + * + * "NOTE: 128BPE Format Color Buffer ( render target ) MUST be either + * TileX or Linear." + * + * This is necessary all the way back to 965, but is permitted on Gen7+. + */ + if (ISL_DEV_GEN(dev) < 7 && isl_format_get_layout(info->format)->bpb >= 128) + *flags &= ~ISL_TILING_Y0_BIT; } /** |