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authorJason Ekstrand <[email protected]>2016-07-08 17:24:19 -0700
committerJason Ekstrand <[email protected]>2016-07-13 11:47:37 -0700
commit0bd3a7e931b0cfd5aa81f37c43c330d6ae656a49 (patch)
treeb627e15a5c2dbbafe116dd96ca10d0eabff02c48 /src/intel/isl/isl.c
parent4b62c19c323f79e7cc4feff5845996e8dde8daaf (diff)
isl: Change the physical size of a W-tile to 128x32
Reviewed-by: Chad Versace <[email protected]>
Diffstat (limited to 'src/intel/isl/isl.c')
-rw-r--r--src/intel/isl/isl.c14
1 files changed, 12 insertions, 2 deletions
diff --git a/src/intel/isl/isl.c b/src/intel/isl/isl.c
index c710bca6d29..4205c1c03a4 100644
--- a/src/intel/isl/isl.c
+++ b/src/intel/isl/isl.c
@@ -133,10 +133,20 @@ isl_tiling_get_info(const struct isl_device *dev,
break;
case ISL_TILING_W:
- /* XXX: Should W tile be same as Y? */
assert(bs == 1);
logical_el = isl_extent2d(64, 64);
- phys_B = isl_extent2d(64, 64);
+ /* From the Broadwell PRM Vol 2d, RENDER_SURFACE_STATE::SurfacePitch:
+ *
+ * "If the surface is a stencil buffer (and thus has Tile Mode set
+ * to TILEMODE_WMAJOR), the pitch must be set to 2x the value
+ * computed based on width, as the stencil buffer is stored with two
+ * rows interleaved."
+ *
+ * This, together with the fact that stencil buffers are referred to as
+ * being Y-tiled in the PRMs for older hardware implies that the
+ * physical size of a W-tile is actually the same as for a Y-tile.
+ */
+ phys_B = isl_extent2d(128, 32);
break;
case ISL_TILING_Yf: