diff options
| author | Rafael Antognolli <[email protected]> | 2019-04-16 16:31:06 +0300 |
|---|---|---|
| committer | Topi Pohjolainen <[email protected]> | 2019-04-24 08:56:42 +0300 |
| commit | f2041d2a9266ec14270b6da9bf9ce2b54d555ebd (patch) | |
| tree | 2e8ffb14c196869cfb582b2a7a87c7b52d44ff16 /src/intel/isl/isl.c | |
| parent | 45957c05b06f6e05820a87276b682af110bb13a9 (diff) | |
intel/isl: Resize clear color buffer to full cacheline
Fixes MCS fast clear gpu hangs with Vulkan CTS on ICL in CI.
v2 (Nanley): In the title s/Align/Resize/
Reviewed-by: Kenneth Graunke <[email protected]>
Reviewed-by: Nanley Chery <[email protected]>
Tested-by: Topi Pohjolainen <[email protected]>
Signed-off-by: Rafael Antognolli <[email protected]>
Diffstat (limited to 'src/intel/isl/isl.c')
| -rw-r--r-- | src/intel/isl/isl.c | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/src/intel/isl/isl.c b/src/intel/isl/isl.c index 6b9e6c9e0f0..acfed5119ba 100644 --- a/src/intel/isl/isl.c +++ b/src/intel/isl/isl.c @@ -122,7 +122,8 @@ isl_device_init(struct isl_device *dev, dev->ss.size = RENDER_SURFACE_STATE_length(info) * 4; dev->ss.align = isl_align(dev->ss.size, 32); - dev->ss.clear_color_state_size = CLEAR_COLOR_length(info) * 4; + dev->ss.clear_color_state_size = + isl_align(CLEAR_COLOR_length(info) * 4, 64); dev->ss.clear_color_state_offset = RENDER_SURFACE_STATE_ClearValueAddress_start(info) / 32 * 4; |