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authorSamuel Iglesias Gonsálvez <[email protected]>2019-02-19 13:06:25 +0100
committerLionel Landwerlin <[email protected]>2019-02-22 11:45:45 +0000
commitbd2c5a8203851aa88ddbabe78408416db321c95d (patch)
treeced5bff139297b91d13428d3d964a84647c0d55d /src/intel/isl/isl.c
parent2ee197d6e84aa37638d423363aca183952816067 (diff)
isl: the display engine requires 64B alignment for linear surfaces
v2: Add PRM quote (Lionel) Signed-off-by: Samuel Iglesias Gonsálvez <[email protected]> Reviewed-by: Lionel Landwerlin <[email protected]>
Diffstat (limited to 'src/intel/isl/isl.c')
-rw-r--r--src/intel/isl/isl.c8
1 files changed, 8 insertions, 0 deletions
diff --git a/src/intel/isl/isl.c b/src/intel/isl/isl.c
index 5c34efb9a13..6b9e6c9e0f0 100644
--- a/src/intel/isl/isl.c
+++ b/src/intel/isl/isl.c
@@ -1519,6 +1519,14 @@ isl_surf_init_s(const struct isl_device *dev,
}
}
base_alignment_B = isl_round_up_to_power_of_two(base_alignment_B);
+
+ /* From the Skylake PRM Vol 2c, PLANE_STRIDE::Stride:
+ *
+ * "For Linear memory, this field specifies the stride in chunks of
+ * 64 bytes (1 cache line)."
+ */
+ if (isl_surf_usage_is_display(info->usage))
+ base_alignment_B = MAX(base_alignment_B, 64);
} else {
const uint32_t total_h_tl =
isl_align_div(phys_total_el.h, tile_info.logical_extent_el.height);