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authorKenneth Graunke <kenneth@whitecape.org>2018-01-02 14:26:41 -0800
committerKenneth Graunke <kenneth@whitecape.org>2018-01-09 10:13:33 -0800
commit8eadc2fb8fe395ea0a8202217bd5545978962d1d (patch)
tree7797386a6773339af84f0ff951b446f73e013de4 /src/intel/genxml
parent5e7d06fcb0c1f11373ff940670744486a467af93 (diff)
intel: Apply Geminilake "Barrier Mode" workaround.
Apparently, Geminilake requires you to whack a chicken bit to select either compute or tessellation mode for barriers. The recommendation is to switch between them at PIPELINE_SELECT time. We may not need to do this all the time, but I don't know that it hurts either. PIPELINE_SELECT is already a pretty giant stall. This appears to fix hangs in tessellation control shaders with barriers on Geminilake. Note that this requires a corresponding kernel change, drm/i915: Whitelist SLICE_COMMON_ECO_CHICKEN1 on Geminilake. in order for the register write to actually happen. Without an updated kernel, this register write will be noop'd and the fix will not work. Reviewed-by: Rafael Antognolli <rafael.antognolli@intel.com>
Diffstat (limited to 'src/intel/genxml')
-rw-r--r--src/intel/genxml/gen9.xml8
1 files changed, 8 insertions, 0 deletions
diff --git a/src/intel/genxml/gen9.xml b/src/intel/genxml/gen9.xml
index 1422463693d..f07ed748ac7 100644
--- a/src/intel/genxml/gen9.xml
+++ b/src/intel/genxml/gen9.xml
@@ -3710,6 +3710,14 @@
<field name="Color Compression Disable Mask" start="31" end="31" type="bool"/>
</register>
+ <register name="SLICE_COMMON_ECO_CHICKEN1" length="1" num="0x731c">
+ <field name="GLK Barrier Mode" start="7" end="7" type="uint">
+ <value name="GLK_BARRIER_MODE_GPGPU" value="0"/>
+ <value name="GLK_BARRIER_MODE_3D_HULL" value="1"/>
+ </field>
+ <field name="GLK Barrier Mode Mask" start="23" end="23" type="bool"/>
+ </register>
+
<register name="GFX_ARB_ERROR_RPT" length="1" num="0x40a0">
<field name="TLB Page Fault Error" start="0" end="0" type="bool"/>
<field name="RSTRM PAVP Read Invalid" start="1" end="1" type="bool"/>