diff options
| author | Anuj Phogat <[email protected]> | 2018-08-27 16:16:58 -0700 |
|---|---|---|
| committer | Anuj Phogat <[email protected]> | 2018-09-21 14:40:04 -0700 |
| commit | 5eb173304bd1cebdde0617bcc42cd4dca0b8c880 (patch) | |
| tree | 9b14cd353d164d806db7b26db73377ec450accf4 /src/intel/genxml | |
| parent | afb7c6b301ea4275d64498a0b62a908777cb9b24 (diff) | |
anv/icl: Set Enabled Texel Offset Precision Fix bit
h/w specification requires this bit to be always set.
Suggested-by: Kenneth Graunke <[email protected]>
Signed-off-by: Anuj Phogat <[email protected]>
Reviewed-by: Kenneth Graunke <[email protected]>
Diffstat (limited to 'src/intel/genxml')
| -rw-r--r-- | src/intel/genxml/gen11.xml | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/src/intel/genxml/gen11.xml b/src/intel/genxml/gen11.xml index 1b3befbbfc9..c69d7dc89c2 100644 --- a/src/intel/genxml/gen11.xml +++ b/src/intel/genxml/gen11.xml @@ -3640,4 +3640,9 @@ <field name="Headerless Message for Pre-emptable Contexts Mask" start="21" end="21" type="bool"/> </register> + <register name="HALF_SLICE_CHICKEN7" length="1" num="0x0e194"> + <field name="Enabled Texel Offset Precision Fix" start="1" end="1" type="bool"/> + <field name="Enabled Texel Offset Precision Fix Mask" start="17" end="17" type="bool"/> + </register> + </genxml> |