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authorFrancisco Jerez <[email protected]>2019-07-17 18:30:45 -0700
committerFrancisco Jerez <[email protected]>2019-08-12 13:17:58 -0700
commit03cba9f5d9ae339a49dc9fe9f4e3243c88f999d0 (patch)
tree9187a2e613c34f7e25aa252b61687a4f1a7ccc78 /src/intel/genxml/gen9.xml
parent9406b3a5c16fd034d2f2db828f2f833c336683f9 (diff)
intel/genxml: Add GT_MODE hashing defs for Gen9.
Reviewed-by: Kenneth Graunke <[email protected]>
Diffstat (limited to 'src/intel/genxml/gen9.xml')
-rw-r--r--src/intel/genxml/gen9.xml17
1 files changed, 17 insertions, 0 deletions
diff --git a/src/intel/genxml/gen9.xml b/src/intel/genxml/gen9.xml
index 9df7cd82738..0d037489df9 100644
--- a/src/intel/genxml/gen9.xml
+++ b/src/intel/genxml/gen9.xml
@@ -6477,6 +6477,23 @@
<field name="Color Compression Disable Mask" start="31" end="31" type="bool"/>
</register>
+ <register name="GT_MODE" length="1" num="0x7008">
+ <field name="Subslice Hashing" start="8" end="9" type="uint">
+ <value name="8x8" value="0"/>
+ <value name="16x4" value="1"/>
+ <value name="8x4" value="2"/>
+ <value name="16x16" value="3"/>
+ </field>
+ <field name="Subslice Hashing Mask" start="24" end="25" type="int"/>
+ <field name="Slice Hashing" start="11" end="12" type="uint">
+ <value name="NORMAL" value="0"/>
+ <value name="DISABLED" value="1"/>
+ <value name="32x16" value="2"/>
+ <value name="32x32" value="3"/>
+ </field>
+ <field name="Slice Hashing Mask" start="27" end="28" type="int"/>
+ </register>
+
<register name="CL_INVOCATION_COUNT" length="2" num="0x2338">
<field name="CL Invocation Count Report" start="0" end="63" type="uint"/>
</register>