diff options
| author | Jordan Justen <[email protected]> | 2016-04-02 01:25:05 -0700 |
|---|---|---|
| committer | Jordan Justen <[email protected]> | 2016-05-17 13:04:03 -0700 |
| commit | ff417388719828b3b5f0c9e3c0b076e9cff99ff7 (patch) | |
| tree | a6966c5f7d87f9dd540dc366eb462f77dc1474d1 /src/intel/genxml/gen75.xml | |
| parent | 47b390fe45e5e6f982c60b58985892438959cd8e (diff) | |
genxml/hsw: Add L3 cache control registers
These were added to the i965 driver in
5912da45a69923afa1b7f2eb5bb371d848813c41.
Signed-off-by: Jordan Justen <[email protected]>
Reviewed-by: Jason Ekstrand <[email protected]>
Diffstat (limited to 'src/intel/genxml/gen75.xml')
| -rw-r--r-- | src/intel/genxml/gen75.xml | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/src/intel/genxml/gen75.xml b/src/intel/genxml/gen75.xml index 698d93f12ae..2258dee3960 100644 --- a/src/intel/genxml/gen75.xml +++ b/src/intel/genxml/gen75.xml @@ -2932,4 +2932,12 @@ <field name="T Low Bandwidth" start="21" end="21" type="uint"/> </register> + <register name="SCRATCH1" length="1" num="0xb038"> + <field name="L3 Atomic Disable" start="27" end="27" type="uint"/> + </register> + + <register name="CHICKEN3" length="1" num="0xe49c"> + <field name="L3 Atomic Disable" start="6" end="6" type="uint"/> + </register> + </genxml> |